Abstract: Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

Abstract: Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

Abstract: A tool that a user may employ to assemble the components of a circuit in a floor plan design. The tool provides a user interface that displays the placement of blocks in a floor plan design, and the routing of wires among the blocks. When the designer moves the placement of a target block, the user interface automatically moves any adjacent blocks that would impede the movement of the target block and any block that would impede a block moved in response to the movement of the target block. The user interface may also respond to movement of a target block by showing how various features of the circuit will change as a result of the move. Thus, the user interface may show that moving one block closer to another block will create undesired wiring congestion in the circuit. The user interface also may show when moving a block will result in wiring connections that are too long to maintain a desired voltage level.

Abstract: A method estimates the capacitance effects of an interconnect prior to routing of an integrated circuit (IC) design, as follows. The design is divided into areas. Capacitance effects for each area are estimated based on the congestion ratios within the area. The congestion ratios for each area are derived from estimations of the demand for routing resources in each area for each net in the net-list included in the IC design. Coupling vectors are derived for each area from the congestion ratios. Capacitance effects for each area are then estimated by looking up a database using the coupling vectors. The resulting per-area capacitance effects are then used to estimate capacitance in an interconnect traversing the area. The total capacitance effects due to an interconnect traversing multiple areas is determined by applying the per-area capacitance effects for the areas to the dimensions of portions of the interconnect traversing each of the areas.

Abstract: A method estimates the capacitance effects of an interconnect prior to routing of an integrated circuit (IC) design, as follows. The design is divided into areas. Capacitance effects for each area are estimated based on the congestion ratios within the area. The congestion ratios for each area are derived from estimations of the demand for routing resources in each area for each net in the net-list included in the IC design. Coupling vectors are derived for each area from the congestion ratios. Capacitance effects for each area are then estimated by looking up a database using the coupling vectors. The resulting per-area capacitance effects are then used to estimate capacitance in an interconnect traversing the area. The total capacitance effects due to an interconnect traversing multiple areas is determined by applying the per-area capacitance effects for the areas to the dimensions of portions of the interconnect traversing each of the areas.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.