Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create multiple trenches and pads at the same time. After vias are made at the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer with excess conductive metal in the dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.

Abstract: Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal hard mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create trenches and pads for vias at the same time. After vias are made on the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer in the respective dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.

Abstract: A packaging substrate is disclosed in the present invention, which includes a substrate body having a first surface and an opposite second surface. The first surface has a first cavity, and the second surface has a second cavity. The first cavity corresponds to and is interlinked to the second cavity. In order to provide a space for disposing a chip, the dimension of the second cavity is larger than that of the first cavity, such that there is a step at the interlinking region between the first cavity and the second cavity. Additionally, a plurality of wire bonding pads are disposed on the first surface around the first cavity. A package structure comprising the packaging substrate and the application thereof are also provided in the present invention.

Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.

Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.

Abstract: A method of plating a metal layer over isolated pads on a semiconductor package substrate is proposed. This substrate is formed with a plurality of conductive blind vias. The isolated pads are formed on a surface of the substrate, each having a plating line extending towards one blind via but electrically insulated from the blind via by an electrically insulating region. A conductive film covers the surface of the substrate having the isolated pads, and a photoresist layer is formed over the conductive film. The photoresist layer has openings for exposing a portion of the conductive film covering the isolated pads. The exposed portion of the conductive film is removed, to allow a metal layer to be plated on the isolated pads. Then, the photoresist layer and the remainder of the conductive film are removed, and the electrical insulation between the isolated pads and the blind vias is restored.

Abstract: A method of plating a metal layer over isolated pads on a semiconductor package substrate is proposed. This substrate is formed with a plurality of conductive blind vias. The isolated pads are formed on a surface of the substrate, each having a plating line extending towards one blind via but electrically insulated from the blind via by an electrically insulating region. A conductive film covers the surface of the substrate having the isolated pads, and a photoresist layer is formed over the conductive film. The photoresist layer has openings for exposing a portion of the conductive film covering the isolated pads. The exposed portion of the conductive film is removed, to allow a metal layer to be plated on the isolated pads. Then, the photoresist layer and the remainder of the conductive film are removed, and the electrical insulation between the isolated pads and the blind vias is restored.

Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.