Patents by Inventor Chih-Liang Hu

Chih-Liang Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11521862
    Abstract: A process for batch fabrication of circuit components is disclosed via simultaneously packaging multiple circuit component dice in a matrix. Each die has electrodes on its tops and bottom surfaces to be electrically connected to a corresponding electrical terminal of the circuit component it's packaged in. For each circuit component in the matrix, the process forms preparative electrical terminals on a copper substrate. Component dice are pick-and-placed onto the copper substrate with their bottom electrodes landing on corresponding preparative electrical terminal. Horizontal conductor plates are then placed horizontally on top of the circuit component dice, with bottom surface at one end of each plate landing on the dice's top electrode. An opening is formed at the opposite end and has vertical conductive surfaces.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 6, 2022
    Inventor: Chih-liang Hu
  • Patent number: 10600703
    Abstract: A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further formin
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 24, 2020
    Inventor: Chih-liang Hu
  • Publication number: 20190228985
    Abstract: A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further formin
    Type: Application
    Filed: April 5, 2019
    Publication date: July 25, 2019
    Inventor: Chih-liang HU
  • Publication number: 20190187287
    Abstract: A process for batch fabrication of circuit component is disclosed via simultaneously packaging multiple circuit component dice in a matrix. Each die has electrodes on its tops and bottom surfaces to be electrically connected to a corresponding electrical terminal of the circuit component it's packaged in. For each circuit component in the matrix, the process forms preparative electrical terminals on a copper substrate. Component dice are pick-and-placed onto the copper substrate with their bottom electrodes landing on corresponding preparative electrical terminal. Horizontal conductor plates are then placed horizontally on top of the circuit component dice, with bottom surface at one end of each plate landing on the dice's top electrode. An opening is formed at the opposite end and has vertical conductive surfaces.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Inventor: Chih-liang Hu
  • Patent number: 10256116
    Abstract: A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further formin
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 9, 2019
    Inventor: Chih-liang Hu
  • Publication number: 20170287729
    Abstract: A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further formin
    Type: Application
    Filed: March 30, 2017
    Publication date: October 5, 2017
    Inventor: Chih-liang HU
  • Patent number: 9735138
    Abstract: A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts; (b) bonding first and second terminal contacts of an electronic die to the die contacts, respectively; and (c) forming an insulator layer on the first surface of the metal substrate to encapsulate the die and the die contacts after step (b).
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 15, 2017
    Inventor: Chih-Liang Hu
  • Patent number: 9515047
    Abstract: A method for manufacturing circuit component package is disclosed. The method first forms copper circuits on a single-sided printed circuit board, and prints an electrically conductive paste on a plurality of predetermined locations on the copper circuits before positioning circuit dice of the circuit components on the locations printed with the electrically conductive paste. The method then forms a plurality of surface copper bumps on a copper plate, and prints the electrically conductive paste on each of the copper bumps. Then position and fit the printed circuit board on which the circuit dice are positioned relative to the copper plate on which the electrically conductive paste is printed such that each of the circuit dice aligns with the corresponding copper bump printed with the electrically conductive paste.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 6, 2016
    Inventor: Chih-liang Hu
  • Publication number: 20160268228
    Abstract: A method for manufacturing circuit component package is disclosed. The method first forms copper circuits on a single-sided printed circuit board, and prints an electrically conductive paste on a plurality of predetermined locations on the copper circuits before positioning circuit dice of the circuit components on the locations printed with the electrically conductive paste. The method then forms a plurality of surface copper bumps on a copper plate, and prints the electrically conductive paste on each of the copper bumps. Then position and fit the printed circuit board on which the circuit dice are positioned relative to the copper plate on which the electrically conductive paste is printed such that each of the circuit dice aligns with the corresponding copper bump printed with the electrically conductive paste.
    Type: Application
    Filed: March 10, 2015
    Publication date: September 15, 2016
    Inventor: Chih-liang Hu
  • Publication number: 20160254216
    Abstract: A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts; (b) bonding first and second terminal contacts of an electronic die to the die contacts, respectively; and (c) forming an insulator layer on the first surface of the metal substrate to encapsulate the die and the die contacts after step (b).
    Type: Application
    Filed: October 23, 2015
    Publication date: September 1, 2016
    Inventor: Chih-Liang HU
  • Patent number: 6989559
    Abstract: A discrete circuit component is made from a substrate with the first and second surfaces thereof each having a corresponding matrix of electrically conductive segments. A plated through-hole connects each of the conductive segments of each the first and second conductive segments electrically. The through-hole is first clogged and then subsequently cleared of clogging in the fabrication stages.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: January 24, 2006
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Wen-Long Chen, Cheng-Chieh Yang, Chih-Liang Hu
  • Patent number: 6870261
    Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: March 22, 2005
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chih-Liang Hu, Wen-Long Chen, Pan-Nan Chen, Ming-Chong Liang, Cheen-Hai Yu
  • Patent number: 6818541
    Abstract: A method for fabricating metal bonding for a semiconductor circuit component employing prescribed feed of metal ball is disclosed. The method comprises the steps of, first, placing a metal ball at the metallization site on the surface of the circuit die of the component; then, melting the metal ball on the site; and subsequently solidifying the molten metal and forming a metal bump at the site. A circuit die having formed with one or more metal bumps can then be made into a circuit component featuring stable and reliable electrical leads and suitable to be utilized as large power rating yet with reduced component size in electronic equipment.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: November 16, 2004
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Cheng-Chieh Yang, Wen-Long Chen, Yao-Huang Tsai, Chih-Liang Hu, Pan-Nan Chen
  • Publication number: 20040198043
    Abstract: process for fabricating a discrete circuit component on a substrate having fabrication stage clogged through-holes is disclosed. The first surface of the substrate has a matrix of dice surface trace sets each having a first and a second electrically conductive segments. The second surface of the substrate has a corresponding matrix of soldering surface trace sets each having a first and a second electrically conductive segments. A plated through-hole electrically connects each of the first and second conductive segments of each of the dice surface trace sets respectively to the first and second conductive segments of the corresponding soldering surface trace set.
    Type: Application
    Filed: May 8, 2003
    Publication date: October 7, 2004
    Inventors: Wen-Long Chen, Cheng-Chieh Yang, Chih-Liang Hu
  • Publication number: 20040185650
    Abstract: A method for fabricating metal bonding for a semiconductor circuit component employing prescribed feed of metal ball is disclosed. The method comprises the steps of, first, placing a metal ball at the metallization site on the surface of the circuit die of the component; then, melting the metal ball on the site; and subsequently solidifying the molten metal and forming a metal bump at the site. A circuit die having formed with one or more metal bumps can then be made into a circuit component featuring stable and reliable electrical leads and suitable to be utilized as large power rating yet with reduced component size in electronic equipment.
    Type: Application
    Filed: April 21, 2003
    Publication date: September 23, 2004
    Inventors: Cheng-Chieh Yang, Wen-Long Chen, Yao-Huang Tsai, Chih-Liang Hu, Pan-Nan Chen
  • Publication number: 20040183196
    Abstract: A method for fabricating metal bonding for a semiconductor circuit component employing prescribed feed of metal ball is disclosed. The method comprises the steps of, first, placing a metal ball at the metallization site on the surface of the circuit die of the component; then, melting the metal ball on the site; and subsequently solidifying the molten metal and forming a metal bump at the site. A circuit die having formed with one or more metal bumps can then be made into a circuit component featuring stable and reliable electrical leads and suitable to be utilized as large power rating yet with reduced component size in electronic equipment.
    Type: Application
    Filed: December 16, 2003
    Publication date: September 23, 2004
    Inventors: Cheng-Chieh Yang, Wen-Long Chen, Yao-Huang Tsai, Chih-Liang Hu, Pan-Nan Chen
  • Publication number: 20040164406
    Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.
    Type: Application
    Filed: February 26, 2003
    Publication date: August 26, 2004
    Inventors: Chih-Liang Hu, Wen-Long Chen, Pan-Nan Chen, Ming-Chong Liang, Cheen-Hai Yu