Patents by Inventor Chih-Lieh CHEN

Chih-Lieh CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954841
    Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Lieh Chen, Cheng-Kang Hu, Cheng-Lung Wu, Jiun-Rong Pai
  • Publication number: 20220292667
    Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 15, 2022
    Inventors: Chih-Lieh CHEN, Cheng-Kang HU, Cheng-Lung WU, Jiun-Rong PAI
  • Patent number: 11423526
    Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Lieh Chen, Cheng-Kang Hu, Cheng-Lung Wu, Jiun-Rong Pai
  • Publication number: 20220156911
    Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Chih-Lieh CHEN, Cheng-Kang HU, Cheng-Lung WU, Jiun-Rong PAI