Patents by Inventor Chih-Lin Huang
Chih-Lin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978669Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.Type: GrantFiled: January 4, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20240145470Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Lung-Kun CHU, Mao-Lin HUANG, Chung-Wei HSU, Jia-Ni YU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20240135078Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: ApplicationFiled: January 4, 2024Publication date: April 25, 2024Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Patent number: 11961840Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.Type: GrantFiled: August 9, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240120402Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.Type: ApplicationFiled: November 19, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
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Publication number: 20240113195Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.Type: ApplicationFiled: February 22, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11948987Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.Type: GrantFiled: September 9, 2020Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11942478Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.Type: GrantFiled: May 6, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
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Patent number: 11942513Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.Type: GrantFiled: January 10, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
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Publication number: 20240096880Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.Type: ApplicationFiled: November 16, 2023Publication date: March 21, 2024Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
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Publication number: 20240096994Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.Type: ApplicationFiled: February 10, 2023Publication date: March 21, 2024Inventors: Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20240089607Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.Type: ApplicationFiled: May 29, 2023Publication date: March 14, 2024Applicant: HTC CorporationInventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
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Patent number: 11920778Abstract: A ventilation fan includes a housing having an opening, a grille structure positioned to cover the opening, a fan module provided in the housing and a function module. The grille structure includes a base defining an outlet, and a grille support spaced apart from the base and connected by the connecting columns A radial inlet is formed between the base and the grille support is in communication with the outlet. The base includes a holder having a holding opening axially downward and faced away from the housing. The function module is disposed within the holder through the holding opening.Type: GrantFiled: September 30, 2022Date of Patent: March 5, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Hsiang Huang, Yen-Lin Chen, Chih-Hua Lin
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Patent number: 11915954Abstract: A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.Type: GrantFiled: January 30, 2023Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Huang, Cheng-Lung Wu, Zheng-Lin He, Yang-Ann Chu, Jiun-Rong Pai, Hsuan Lee
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Publication number: 20220384246Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Ying-Cheng CHUANG, Chung-Lin HUANG, Lai-Cheng TIEN, Chih-Lin HUANG, Zhi-Yi HUANG, Hsu CHIANG
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Patent number: 11450553Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.Type: GrantFiled: August 13, 2020Date of Patent: September 20, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Ying-Cheng Chuang, Chung-Lin Huang, Lai-Cheng Tien, Chih-Lin Huang, Zhi-Yi Huang, Hsu Chiang
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Publication number: 20220051931Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.Type: ApplicationFiled: August 13, 2020Publication date: February 17, 2022Inventors: Ying-Cheng CHUANG, Chung-Lin HUANG, Lai-Cheng TIEN, Chih-Lin HUANG, Zhi-Yi HUANG, Hsu CHIANG
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Publication number: 20120028151Abstract: A method is provided for fuel cell system control. In this method, the operation of a fuel cell system is divided into several modes, and the operation mode of the fuel cell system can be decided according to voltage signals, current signals and temperature signals of the fuel cell system. Moreover, a fuel cell system using this control method is also provided.Type: ApplicationFiled: September 29, 2010Publication date: February 2, 2012Applicant: Institute of Nuclear Energy Research Atomic Energy Council, Executive YuanInventors: Shih-Wei Lin, Charn-Ying Chen, Chih-Lin Huang
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Patent number: 8073192Abstract: Methods are described for predicting the percentage of latewood and specific gravity of lumber independent of moisture content using image analysis of the lumber surfaces.Type: GrantFiled: December 24, 2008Date of Patent: December 6, 2011Assignee: Weyerhaeuser NR CompanyInventors: Chih-Lin Huang, Greg J Leaf
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Publication number: 20110171550Abstract: A method for controlling a fuel cell system is provided. In this method, the operation of a fuel cell system is divided into several modes, and the operation mode of the fuel cell system is determined according to voltage signals, current signals, and temperature signals of the fuel cell system. Moreover, a fuel cell system using the control method is also provided.Type: ApplicationFiled: July 7, 2010Publication date: July 14, 2011Applicant: Institute of Nuclear Energy Research Atomic Energy Council, Executive YuanInventors: SHIH-WEI LIN, Charn-Ying Chen, Chih-Lin Huang, Chi-Yuan Chang