Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: A method of monitoring wear of a buffer includes holding a pipe for transporting a fluid and an electrical cable using a buffer placed on a support plate. The buffer includes a base, a plurality of fingers, and a roller contacting the support plate. The plurality of fingers includes a first finger, a second finger, and a third finger. The first finger and the second finger define a first cavity for receiving the pipe, and the second finger and the third finger defines a second cavity for receiving the electrical cable. The method includes detecting acoustic waves generated by the roller on the support plate. The method further includes analyzing changes in frequencies of the acoustic waves to determine an extent of the wear of the roller over time. The method includes triggering an alert when an increase in the frequencies of the acoustic waves exceeds a pre-determined threshold value.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard contact disposed within a dielectric structure on a substrate. An oversized contact is disposed within the dielectric structure and is laterally separated from the standard contact. The oversized contact has a larger width than the standard contact. An interconnect wire vertically contacts the oversized contact. A through-substrate via (TSV) vertically extends through the substrate. The TSV physically and vertically contacts the oversized contact or the interconnect wire. The TSV vertically overlaps the oversized contact or the interconnect wire over a non-zero distance.

Abstract: A photodetecting device is provided. The photodetecting device includes a silicon substrate, a germanium absorption region, and a plurality of microstructures. The silicon substrate includes a first surface and a second surface. The germanium absorption region is formed proximal to the first surface of the silicon substrate, and the germanium absorption region is configured to absorb photons and to generate photo-carriers. The plurality of microstructures are formed over the second surface of the silicon substrate, and the plurality of microstructures are configured to direct an optical signal towards the germanium absorption region. A system including an optical transmitter and an optical receiver is also provided.

Abstract: An optical apparatus includes: a substrate having a first material; an absorption region having a second material different from the first material, the absorption region configured to absorb photons and to generate photo-carriers including electrons and holes in response to the absorbed photons; a first well region surrounding the absorption region and arranged between the absorption region and the substrate, the first well region being doped with a first polarity; and one or more switches each controlled by a respective control signal, the one or more switches each configured to collect at least a portion of the photo-carriers based on the respective control signal and to provide the portion of the photo-carriers to a respective readout circuit.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

Abstract: The present disclosure provides systems and methods that leverage machine learning to perform user input motion prediction. In particular, the systems and methods of the present disclosure can include and use a machine-learned motion prediction model that is trained to receive motion data indicative of motion of a user input object and, in response to receipt of the motion data, output predicted future locations of the user input object. The user input object can be a finger of a user or a stylus operated by the user. The motion prediction model can include a deep recurrent neural network.

Abstract: A storage server management system includes a management database for storing rack data and storage server data, wherein the rack data includes rack identifications and coordinates of multiple storage servers and the storage server data includes media access control addresses, model name and rail identifications of the multiple storage servers, multiple racks for containing the multiple storage servers, a dynamic host configuration protocol server for configuring the internet protocol addresses to the multiple storage servers, and a management console for generating a rack location map according to the rack data and the storage server data.

Abstract: A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

Abstract: A nozzle assembly for use in liquid-dispensing system, the nozzle assembly includes a pipe having lumens; a body, an end of the pipe being mounted to the body; the pipe having a wall and a septum, the wall enclosing a space, the septum dividing the space enclosed by the wall into the lumens; each of the lumens being correspondingly terminated in an orifice such that a liquid is escapable from each lumen through the corresponding orifice and is thereby dispensable from the nozzle assembly.

Abstract: A method for identifying a signal transmission device includes: reading attribute information from a memory device by a first device of a signal processing system, wherein the attribute information records information regarding at least one attribute of the signal transmission device that is coupled between the first device and a second device of the signal processing system; determining the at least one attribute of the signal transmission device by the first device according to the attribute information; and setting a maximum value or a minimum value of a signal output by the first device or the second device according to the at least one attribute.

Abstract: A biomimetic system is provided for evaluating an effect of a test sample in vitro, and includes at least one organ chip, at least one medium container, a liquid pump, a nebulizer, a gas pump, and a chamber device. The liquid pump is provided to drive a liquid medium in the medium container to flow into a lower sub-channel of the organ chip and then to be discharged back into the medium container. The nebulizer is provided for atomizing a test solution including the test sample into an aerosol. The gas pump is provided to generate a pressurized gas which force the aerosol to flow out of a chamber of the chamber device and then to flow through an upper sub-channel of the organ chip.

Abstract: A recoater collision prediction and calibration method for additive manufacturing and a system thereof are provided.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: Systems, methods and apparatus for dispensing of paper products. A dispenser comprising a housing comprising a product holding area defined by a front, back and two sides, and a dispenser throat defining an opening through the housing; a motor coupled to the rolled product and configured to rotate the rolled product in first and second directions; and a feed mechanism having a first side opening and a second side opening different from the first side opening, wherein both the first side and second side openings are different from that dispenser throat, and wherein the first side opening is configured to accept the tail when the rolled product has a first orientation and is rotated in the first direction and the second side opening is configured to accept the tail when the rolled product has a second orientation and is rotated in the second direction.

Abstract: An apparatus and method for providing a filtering false photon count events for each pixel in a DTOF sensor array are disclosed herein. In some embodiments, the apparatus includes: a light source configured to emit a modulated signal towards the object; a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, wherein the DTOF sensor array comprises a plurality of single-photon avalanche diodes (SPADs); and processing circuitry configured to receive photon event detection signals from a center pixel and a plurality of pixels orthogonally and diagonally adjacent to the center pixel and output a valid photon detection signal, in response to determining whether a sum of the received photon event detection signals is greater than a predetermined threshold.

Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.