Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap enclosed in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: A fan includes a fan hub and multiple blades. At least one blade includes a blade body and two extended blade portions. The two extended blade portions are connected to a first edge and a second edge on the blade body. The first edge and the second edge are opposite to sides of the blade body. In a top view, at least one of the two extended blade portions has a first width that is adjacent to the fan hub, and a second width that is away from the fan hub. The second width is larger than the first width. The second width and the first width are connected by a continuous surface. The width of the continuous surface increases away from the first width.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: A sensor device includes a fingerprint sensing module, configured to sense a first raw image using a first exposure time; and an exposure time adjusting module. The exposure time adjusting module is configured to obtain a first image according to the first raw image; determine whether the first image comprises a flicker noise; and adjust the first exposure time when the first image comprises the flicker noise, so as to mitigate the flicker noise.

Abstract: A sensor device includes a fingerprint sensing module, configured to sense a first raw image using a first exposure time; and an exposure time adjusting module. The exposure time adjusting module is configured to obtain a first image according to the first raw image; determine whether the first image comprises a flicker noise; and adjust the first exposure time when the first image comprises the flicker noise, so as to mitigate the flicker noise.

Abstract: An identification recognition device includes a light emission module, a light sensing module, a pulse scanning unit, a fingerprint scanning unit and a controller. The light sensing module is used to generate first light currents and second light currents according to first reflecting light and second reflecting light. The pulse scanning unit is used to generate data of current variance of the object and the fingerprint scanning unit is used to generate features of fingerprint of the object. The controller is used to control the light emission module to emit the first incident light and to emit the second incident light when the object has a pulse according to the data of current variance of the object, and determine if the object passes the identification recognition test according to the features of fingerprint of the object.

Abstract: An identification recognition device includes a light emission module, a light sensing module, a pulse scanning unit, a fingerprint scanning unit and a controller. The light sensing module is used to generate first light currents and second light currents according to first reflecting light and second reflecting light. The pulse scanning unit is used to generate data of current variance of the object and the fingerprint scanning unit is used to generate features of fingerprint of the object. The controller is used to control the light emission module to emit the first incident light and to emit the second incident light when the object has a pulse according to the data of current variance of the object, and determine if the object passes the identification recognition test according to the features of fingerprint of the object.