Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A service plan generation method performed by a computing device includes: receiving a service request, wherein the service request includes a plurality of feature labels; selecting a plurality of recommended items from an item database according to the plurality of feature labels; calculating a plurality of item failure rates according to a plurality of historical execution records of the plurality of recommended items; calculating a plurality of redo counts corresponding to the plurality of recommended items according to the plurality of item failure rates; generating a plurality of buffer items corresponding to the plurality of recommended items according to the plurality of redo counts; and performing a scheduling according to the plurality of recommended items and the plurality of buffer items to generate a service plan.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: The present disclosure describes a structure including a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate and a method of forming the structure. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

Abstract: A mounting system for an electronic device is disclosed. The mounting system includes a mounting plate; a plurality of fasteners for coupling the mounting plate with the electronic device; a single main gear mounted on the mounting plate; a plurality of secondary gears coupled, respectively, to the plurality of fasteners; and a plurality of intermediate gears mounted on the mounting plate and rotationally coupled between the single main gear and the plurality of secondary gears. Rotation of each of the plurality of secondary gears causes a fastening movement of a respective one of the plurality of fasteners. Simultaneous rotation of the plurality of intermediate gears causes the plurality of secondary gears to rotate simultaneously in response to a single rotational force being received by the main gear. The simultaneous rotation of the plurality of intermediate gears causes a simultaneous fastening movement of the plurality of secondary gears.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A heating structure includes a first cover plate, a second cover plate, a conductive portion; and two first driving electrodes. The conductive portion is connected to the first cover plate and the second cover plate. The first cover plate, the conductive portion, and the second cover plate cooperatively define a channel for carrying a microbead. The channel includes a flow path. The two first driving electrodes are electrically connected to the conductive portion to energize the conductive portion. When the conductive portion is energized, a driving force is generated to drive the microbead away from a sidewall of the conductive portion to the flow path. A nucleic acid detection kit with the detection chip, and a nucleic acid detection device with the nucleic acid detection kit are also disclosed.

Abstract: An electrowetting on dielectric (EWOD) device able to self-detect a movement of a droplet under test includes a detection chip, a power switch module, a detection module, and a determination module. The detection chip includes a channel, several driving electrodes, and a detection electrode. Each driving electrode can couple with the detection electrode to form a driving loop. The power switch module provides one of a first voltage and a second voltage, to rock the droplet along, and a third voltage can also be applied to a specified driving electrode. The detection module computes a capacitance recovery time of the detection voltage changing from a peak voltage to a reference voltage in one cycle of a voltage period. The determination module confirms a position of the droplet based on the recovery time. A method for a self-detecting a movement of the droplet in EWOD device is also disclosed.

Abstract: A film with a first circuit printed on a lower surface, a film insulator and a film with a second circuit printed on an upper surface are mounted on the keyboard. Each of the first and second circuits includes a plurality of contacts. The film insulator defines a plurality of apertures. One of the contacts of the first circuit will be engaged with one of the contacts of the second circuit through one of the apertures defined in the film insulator if a key switch is pressed. The key switch includes a frame defining two vertical slots. A slidable member includes a plate, two hooks projecting downwardly from the plate and each including a barb for engaging with one of the vertical slots and a hollow cylinder projecting downwardly from the plate and defining two vertical slots. A cup includes two barbs projecting radially inwardly therefrom. The hollow cylinder is insertable in the cup. The barbs formed on the cup are engageable in the slots defined in the hollow cylinder.