Abstract: A manufacture method of a deodorization fiber includes: a mixing step including mixing zirconium phosphate and a first dispersant including an amine-group compound in a solvent to form a mixture; a grinding step including grinding the mixture until a D90 particle size of zirconium phosphate is 0.1 ?m to 1.5 ?m to form a grinded mixture; a heating and stirring step including heating and stirring the grinded mixture to uniformly distribute zirconium phosphate and the first dispersant in the solvent to form a deodorant; a blending and pelletizing step including blending and pelletizing the deodorant and polyester to form a fiber masterbatch; and a melt spinning step including melt spinning the fiber masterbatch to form the deodorization fiber. A deodorization fiber is further provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A carrier aggregation circuit includes a signal input terminal, a signal output terminal, a first filter, a first output transform circuit, a second filter, and a second output transform circuit. The signal input terminal receives a radio frequency signal with carrier waves with first and second carrier wave frequencies. The first filter and the second filter are coupled between the signal input terminal and the signal output terminal respectively, and can respectively filter out signals with frequencies other than the first and the second carrier wave frequencies. The first output transform circuit is coupled between the first filter and the signal output terminal, and has an output impedance equivalent to an open circuit at the second carrier frequency. The second output transform circuit is coupled between the second filter and the signal output terminal, and has an output impedance equivalent to an open circuit at the first carrier frequency.

Abstract: A carrier aggregation circuit includes a signal input terminal, a signal output terminal, a first filter, a first output transform circuit, a second filter, and a second output transform circuit. The signal input terminal receives a radio frequency signal with carrier waves with first and second carrier wave frequencies. The first filter and the second filter are coupled between the signal input terminal and the signal output terminal respectively, and can respectively filter out signals with frequencies other than the first and the second carrier wave frequencies. The first output transform circuit is coupled between the first filter and the signal output terminal, and has an output impedance equivalent to an open circuit at the second carrier frequency. The second output transform circuit is coupled between the second filter and the signal output terminal, and has an output impedance equivalent to an open circuit at the first carrier frequency.

Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.

Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.

Abstract: In a bipolar junction transistor (BJT) process, according to the linearity of an implant dosage and the output characteristics of a power amplifier, the implant dosage in the poly-silicon layer is selected and controlled in order to form different power level silicon germanium (SiGe) based power amplifiers. Cost, complexity, and time of IC manufacture are reduced.

Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.

Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.

Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.

Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.

Abstract: During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.

Abstract: During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.