Abstract: A method for forming a patterned mask layer is provided. The method includes forming a layer over a substrate. The method includes forming a first strip structure and a second strip structure over the layer. The method includes forming a spacer layer over the first strip structure, the second strip structure, and the layer. The method includes forming a third strip structure and a fourth strip structure between the first strip part and the second strip part. The connecting part is between the third strip structure and the fourth strip structure. The method includes removing the spacer layer. The first strip structure, the second strip structure, the third strip structure, and the fourth strip structure together form a patterned mask layer.

Abstract: The present invention discloses a data access interface unit comprising: a physical storage device controller for receiving a first control signal from a first storage virtualization controller, and accordingly determining the first storage virtualization controller as the primary controller, and generating a first selection signal; a selector for receiving the first selection signal, and accordingly selecting data and signals from the first storage virtualization controller; and a clock generation circuit for providing a dedicated clock signal to the physical storage device, where when the physical storage device controller receives a re-set signal from a second storage virtualization controller, the physical storage device controller determines the second storage virtualization controller as the new primary controller, and accordingly generates a second selection signal so as to control the selector to select data and signals from the second storage virtualization controller.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Abstract: An integrated circuit includes a set of power rails, a set of active regions, a first set of conductive lines and a first and a second set of vias. The set of power rails is configured to supply a first or second supply voltage, and is on a first level of a back-side of a substrate. The set of active regions is a second level of a front-side of the substrate. The first set of conductive lines extend in a second direction and overlap the set of active regions. The first set of vias is between and electrically couples the set of active regions and the first set of conductive lines together. The second set of vias is between and electrically couples the first set of conductive lines and the set of power rails together.

Abstract: A method for forming a semiconductor structure includes forming first mandrels over a target layer. The method for forming a semiconductor structure also includes forming a first opening to cut off one of the first mandrels. The method for forming a semiconductor structure also includes forming a spacer layer over the first mandrels. The method for forming a semiconductor structure also includes forming second mandrels over the spacer layer and between the first mandrels. The method for forming a semiconductor structure also includes forming a second opening to cut off one of the second mandrels. The method for forming a semiconductor structure also includes etching the spacer layer. The method for forming a semiconductor structure also includes etching the target layer.

Abstract: A method of fabricating an integrated circuit includes fabricating a set of transistors and a dummy via in a front-side of a substrate, performing thinning on a back-side of the substrate opposite from the front-side, fabricating a first set of vias and a first set of conductors on the back-side of a thinned substrate on a first level, the first set of conductors being electrically coupled to the set of transistors by the first set of vias, fabricating a second set of vias on the back-side of the thinned substrate, and depositing a conductive material on the back-side of the thinned substrate on a second level thereby forming a second set of conductors, the second set of conductors being electrically coupled to the first set of conductors by the second set of vias.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Abstract: A method includes bonding a front side surface of a first wafer to a front side of a second wafer; forming a bonding material on a periphery of the first wafer and a periphery of the second wafer; performing a thinning process on the first wafer from a back side surface of the first wafer; after performing the thinning process, performing a trimming process from the back side surface of the first wafer to remove a first portion of the bonding material and partially trim down the periphery of the second wafer from a front side surface of the second wafer.

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Abstract: The present invention discloses a data access interface unit comprising: a physical storage device controller for receiving a first control signal from a first storage virtualization controller, and accordingly determining the first storage virtualization controller as the primary controller, and generating a first selection signal; a selector for receiving the first selection signal, and accordingly selecting data and signals from the first storage virtualization controller; and a clock generation circuit for providing a dedicated clock signal to the physical storage device, where when the physical storage device controller receives a re-set signal from a second storage virtualization controller, the physical storage device controller determines the second storage virtualization controller as the new primary controller, and accordingly generates a second selection signal so as to control the selector to select data and signals from the second storage virtualization controller.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: A method includes bonding a front side surface of a first wafer to a second wafer; performing a multi-trimming process on the first and second wafers from a back side surface of the first wafer, the multi-trimming process comprising: performing a first trimming step from the back side surface of the first wafer to cut through a periphery of the first wafer; performing a second trimming step on the second wafer to partially cut a periphery of the second wafer to form a first step-like structure; and performing a third trimming step on the second wafer to partially cut the periphery of the second wafer to form a second step-like structure connecting down from the first step-like structure; after performing the multi-trimming process, forming a coating material at least over the periphery of the second wafer.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: A method of manufacturing a plurality of via structures includes providing an integrated circuit (IC) photo mask including via features and assist features positioned exclusively along alternating diagonal grid lines of a grid, aligning the IC photo mask with first metal segments of a first metal layer of a semiconductor substrate, the first metal segments having a first spacing corresponding to a first pitch of the grid, performing one or more photolithography processes including the IC photo mask, thereby defining via structure locations corresponding to the via features, and forming via structures at the defined via structure locations.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments.