Patents by Inventor Chih Min Hu
Chih Min Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9030855Abstract: A semiconductor device, a start-up circuit, and an operating method for the same are provided. The start-up circuit comprises a semiconductor unit, a first circuit, a second circuit, a voltage input terminal and a voltage output terminal. The first circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The second circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The semiconductor unit is coupled to a first node between the first circuit and the second circuit. The voltage input terminal is coupled to the semiconductor unit. The voltage output terminal is coupled to a second node between the semiconductor unit and the first circuit.Type: GrantFiled: July 14, 2011Date of Patent: May 12, 2015Assignee: Macronix International Co., Ltd.Inventors: Wing-Chor Chan, Chih-Min Hu, Li-Fan Chen
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Patent number: 8963238Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.Type: GrantFiled: February 26, 2014Date of Patent: February 24, 2015Assignee: Macronix International Co., Ltd.Inventors: Wing Chor Chan, Chih-Min Hu, Shyi-Yuan Wu, Jeng Gong
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Patent number: 8841709Abstract: A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.Type: GrantFiled: April 18, 2012Date of Patent: September 23, 2014Assignee: Macronix International Co., Ltd.Inventors: Wing Chor Chan, Chih Min Hu, Jeng Gong
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Publication number: 20140175544Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: Macronix International Co., Ltd.Inventors: Wing Chor Chan, Chih-Min Hu, Shyi-Yuan Wu, Jeng Gong
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Patent number: 8698240Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.Type: GrantFiled: May 25, 2010Date of Patent: April 15, 2014Assignee: Macronix International Co., Ltd.Inventors: Wing Chor Chan, Chih-Min Hu, Shyi-Yuan Wu, Jeng Gong
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Publication number: 20130277718Abstract: A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wing Chor Chan, Chih Min Hu, Jeng Gong
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Patent number: 8557653Abstract: A method of manufacturing a junction-field-effect-transistor (JFET) device, the method includes the steps of providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between tType: GrantFiled: December 12, 2012Date of Patent: October 15, 2013Assignee: Macronix International Co., Ltd.Inventors: Chih-Min Hu, Chung Yu Hung, Wing Chor Chan, Jeng Gong
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Publication number: 20130015888Abstract: A semiconductor device, a start-up circuit, and an operating method for the same are provided. The start-up circuit comprises a semiconductor unit, a first circuit, a second circuit, a voltage input terminal and a voltage output terminal. The first circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The second circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The semiconductor unit is coupled to a first node between the first circuit and the second circuit. The voltage input terminal is coupled to the semiconductor unit. The voltage output terminal is coupled to a second node between the semiconductor unit and the first circuit.Type: ApplicationFiled: July 14, 2011Publication date: January 17, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wing-Chor Chan, Chih-Min Hu, Li-Fan Chen
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Patent number: 8350304Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.Type: GrantFiled: June 7, 2010Date of Patent: January 8, 2013Assignee: Macronix International Co., Ltd.Inventors: Chih-Min Hu, Chung Yu Hung, Wing Chor Chan, Jeng Gong
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Patent number: 8264056Abstract: A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced.Type: GrantFiled: July 29, 2010Date of Patent: September 11, 2012Assignee: Macronix International Co., Ltd.Inventors: Chung Yu Hung, Chih Min Hu, Wing Chor Chan, Jeng Gong
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Publication number: 20120025278Abstract: A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung Yu Hung, Chih Min Hu, Wing Chor Chan, Jeng Gong
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Publication number: 20110291187Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Inventors: Wing Chor Chan, Chih-Min Hu, Shyi-Yuan Wu, Jeng Gong
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Publication number: 20110220973Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.Type: ApplicationFiled: June 7, 2010Publication date: September 15, 2011Inventors: Chih-Min HU, Chung Yu HUNG, Wing Chor CHAN, Jeng GONG