Abstract: A quad-flat non-leaded (QFN) multichip package and a multichip package are provided. The QFN multichip package includes a lead frame, a first chip, a second chip and a molding compound. The lead frame has a plurality of first leads and second leads alternately arranged with each other. Each first lead includes a first connection portion and a first contact portion. Each second lead includes a second connection portion, a bending part and a second contact portion. The bending part is bent upward such that an interval is formed between the second contact portion and the first contact portion. The first chip is disposed between the first leads and the second leads. The second chip is disposed above the first chip. The molding compound encloses the first chip, the second chip, the first leads and the second leads, and further exposes the lower surfaces of the first and the second leads.

Abstract: A package structure with a heat spreader and manufacturing method thereof is disclosed. The package structure includes a substrate, a ground pad, a heat spreader, a non-conductive adhesive layer, and a pre-solder layer. A die is seated on the substrate, and the ground pad is disposed on the surface of the substrate. The manufacturing method of the package structure includes the following steps: (a) providing the substrate; (b) forming the pre-solder layer on the ground pad by solder paste printing; (c) forming the non-conductive adhesive layer on the substrate surface for being adjacent to the pre-solder layer by adhesive dispensing; (d) disposing the heat spreader onto the non-conductive layer and the pre-solder layer; and (e) heating the non-conductive adhesive layer for solidification and continuing to heat the pre-solder layer for solder reflow so that the heat spreader is adhered to the substrate via the non-conductive adhesive layer and coupled to the ground pad via the pre-solder layer.

Abstract: A package structure with a heat spreader and manufacturing method thereof is disclosed. The package structure includes a substrate, a ground pad, a heat spreader, a non-conductive adhesive layer, and a pre-solder layer. A die is seated on the substrate, and the ground pad is disposed on the surface of the substrate. The manufacturing method of the package structure includes the following steps: (a) providing the substrate; (b) forming the pre-solder layer on the ground pad by solder paste printing; (c) forming the non-conductive adhesive layer on the substrate surface for being adjacent to the pre-solder layer by adhesive dispensing; (d) disposing the heat spreader onto the non-conductive layer and the pre-solder layer; and (e) heating the non-conductive adhesive layer for solidification and continuing to heat the pre-solder layer for solder reflow so that the heat spreader is adhered to the substrate via the non-conductive adhesive layer and coupled to the ground pad via the pre-solder layer.

Abstract: A semiconductor wafer cassette has a first side wall, a second side wall opposite the first side wall, a front surface, and a back surface opposite the front surface. A body defines an internal bay portion with slots for vertically receiving wafers, each slot of the internal bay portion having one support slab. The body also includes two parallel legs for supporting the cassette and a handle for handling the cassette.

Abstract: The present invention discloses a semiconductor wafer cassette, which is able to receive at least one wafer, comprising: a first side wall, a second side wall opposite to the first side wall, a front surface, and a back surface opposite to the front surface; the cassette further comprising a body, the body defining an internal bay portion with slots for vertically receiving a plurality of wafers, each slot of the internal bay portion having one support slab. Moreover, the body also includes two parallel legs for supporting the cassette and a handle for handling the wafer cassette.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.