Abstract: A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

Abstract: A true random number generation system includes a physical unclonable function (PUF) entropy device, a pseudo random number generator, and an encoding circuit. The PUF entropy device is used for generating a random number pool. The pseudo random number generator is used for generating a plurality of first number sequences. The encoding circuit is coupled to the PUF entropy device and the pseudo random number generator for generating a plurality of second number sequences according to the plurality of first number sequences and a plurality of third number sequences selected from the random number pool.

Abstract: An entanglement and recall system includes an antifuse-type PUF cell array and a processing circuit. The antifuse-type PUF cell array generates at least one key. The processing circuit is connected with the antifuse-type PUF cell array to receive the at least one key. While an entanglement action is performed, the processing circuit receives a plain text and the at least one key and generates a cipher text according to the plain text and the at least one key. While a recall action is performed, the processing circuit receives the cipher text and the at least one key and generates the plain text according to the cipher text and the at least one key.

Abstract: A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

Abstract: A true random number generation system includes a physical unclonable function (PUF) entropy device, a pseudo random number generator, and an encoding circuit. The PUF entropy device is used for generating a random number pool. The pseudo random number generator is used for generating a plurality of first number sequences. The encoding circuit is coupled to the PUF entropy device and the pseudo random number generator for generating a plurality of second number sequences according to the plurality of first number sequences and a plurality of third number sequences selected from the random number pool.

Abstract: An entanglement and recall system includes an antifuse-type PUF cell array and a processing circuit. The antifuse-type PUF cell array generates at least one key. The processing circuit is connected with the antifuse-type PUF cell array to receive the at least one key. While an entanglement action is performed, the processing circuit receives a plain text and the at least one key and generates a cipher text according to the plain text and the at least one key. While a recall action is performed, the processing circuit receives the cipher text and the at least one key and generates the plain text according to the cipher text and the at least one key.

Abstract: A radio frequency front end testing method and a radio frequency front end testing device are provided in the present disclosure. The radio frequency front end testing device includes a processing module, a first multiplexing module and a second multiplexing module. The radio frequency front end testing method includes the steps of: transmitting a radio frequency front end testing control signal; switching a plurality of output channel terminals of the first multiplexing module and the second multiplexing module, and providing a testing data signal and a radio frequency front end testing clock signal to a plurality of devices under test; and executing a test procedure on the devices under test based on the testing data signal and the radio frequency front end testing clock signal.

Abstract: A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.

Abstract: An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.

Abstract: A voltage regulator controller is disclosed including: a reference voltage generator for generating a reference voltage; a comparison circuit, coupled with the reference voltage generator, for comparing the reference voltage with an output voltage of a voltage regulator; and a control circuit, coupled with the reference voltage generator and the comparison circuit, for controlling the reference voltage generator to stepwise lower the reference voltage when a power saving command is received by the voltage regulator controller.

Abstract: A voltage regulator controller is disclosed including: a reference voltage generator for generating a reference voltage; a comparison circuit, coupled with the reference voltage generator, for comparing the reference voltage with an output voltage of a voltage regulator; and a control circuit, coupled with the reference voltage generator and the comparison circuit, for controlling the reference voltage generator to stepwise lower the reference voltage when a power saving command is received by the voltage regulator controller.

Abstract: A processing method and a processing apparatus for a digital television are provided. A processing apparatus for a digital television (DTV) to process a DTV stream, comprising: a demultiplexing unit for retrieving a service information from the DTV stream; a memory coupled to the demultiplexing unit for storing the service information; a first processor coupled to the memory for assigning a task by sending a command according to the service information; a second processor coupled to the memory for processing the task according the command; a communication unit coupled to the first processor and the second processor, for receiving the command from the first processor and sending the command to the second processor; and at least one function module coupled to the first processor and the second processor, respectively, controlled by the first processor or the second processor, to process the service information.

Abstract: An optical fiber connector has a rear housing, a reinforcing sleeve and a front housing. The rear housing has a front end, a rear end, a top, a bottom, two opposite sides and two slits longitudinally defined respectively through the top and the bottom at the front end. The reinforcing sleeve is mounted in the rear housing. The front housing is mounted around and the rear housing from the front end of the rear housing and completely covers the slits of the rear housing. The optical fiber connector with the slits has high resistance to the external transverse pulling force and is excellently durable.

Abstract: A processing method and a processing apparatus for a digital television are provided. A processing apparatus for a digital television (DTV) to process a DTV stream, comprising: a demultiplexing unit for retrieving a service information from the DTV stream; a memory coupled to the demultiplexing unit for storing the service information; a first processor coupled to the memory for assigning a task by sending a command according to the service information; a second processor coupled to the memory for processing the task according the command; a communication unit coupled to the first processor and the second processor, for receiving the command from the first processor and sending the command to the second processor; and at least one function module coupled to the first processor and the second processor, respectively, controlled by the first processor or the second processor, to process the service information.

Abstract: An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.

Abstract: A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.