Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.

Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.

Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.

Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.

Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.

Abstract: Methods for inserting dummy boundary cells in an integrated circuit (IC) are provided. A plurality of macros and a top channel are merged into floorplan of the IC. The top channel is arranged between the macros and is filled with a plurality of first dummy boundary cells, and each of the macros includes a macro boundary and a main pattern surrounded by the macro boundary. The first dummy boundary cells within the top channel and between a first macro and a second macro are replaced with a plurality of second dummy boundary cells. The macro boundaries of the first and second macros are formed by the second dummy boundary cells. First gate length of dummy patterns within the first dummy boundary cells is greater than second gate length of dummy patterns within the second dummy boundary cells. The first and second dummy boundary cells are the same size.

Abstract: Methods for inserting dummy boundary cells in an integrated circuit (IC) are provided. A plurality of macros and a top channel are merged into floorplan of the IC. The top channel is arranged between the macros and is filled with a plurality of first dummy boundary cells, and each of the macros includes a macro boundary and a main pattern surrounded by the macro boundary. The first dummy boundary cells within the top channel and between a first macro and a second macro are replaced with a plurality of second dummy boundary cells. The macro boundaries of the first and second macros are formed by the second dummy boundary cells. First gate length of dummy patterns within the first dummy boundary cells is greater than second gate length of dummy patterns within the second dummy boundary cells. The first and second dummy boundary cells are the same size.

Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.

Abstract: A target integrated circuit layout having a plurality of design rules having minimum rules and standard rules used in the target integrated circuit layout is provided. First and second design rule checks are performed, where respective first and second sets of violations of the plurality of design rules and each design rule associated with the first and second sets of violations are recorded. An analysis is performed on the first and second sets of violations, each design rule associated with the first and second sets of violations, and a frequency of usage of each of the plurality of design rules, and a rule usage rate is determined having a number of minimum rules used overall and a number of overall violations of the design rules. An interactive rule database is formed having statistics associated with the rule usage rate for subsequent implementation in an integrated circuit.

Abstract: A semiconductor device disposed on a substrate is provided. The semiconductor device includes two isolation structures, a first conductive layer, a charge trapping layer, a second conductive layer and a gate dielectric layer. The two isolation structures are disposed in the substrate to define an active area. The second conductive layer across the two isolation structures is disposed on the substrate. The first conductive layer is disposed between the two isolation structures and between the second conductive layer and the substrate. The second conductive layer electrically connects with the first conductive layer. The charge trapping layer is disposed on the substrate. The gate dielectric layer is disposed between the first conductive layer and the substrate. An interface between the two isolation structures and the first conductive layer is covered by the charge trapping layer to restrain the kink effect.

Abstract: A method for resetting threshold voltage of a non-volatile memory is provided. The method is suitable for a non-volatile memory having a plurality of memory cells. Each memory cell includes a gate and a charge trapping layer. The method includes erasing the non-volatile memory by Fowler-Nordheim (FN) tunneling effect until erasure saturation. The non-volatile memory has a uniform saturation threshold voltage.

Abstract: A method for erasing a non-volatile memory is provided. The non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell disposed on the first conductive type substrate. The memory cell includes a charge trapping layer and a gate. The erasing method includes the following steps. A first voltage is applied to the gate, a second voltage is applied to the first conductive type substrate, and the second conductive type well is floating. The second voltage is large enough to induce a substrate hot hole effect. The holes are injected into the charge trapping layer by applying the first voltage.

Abstract: A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and the charge storage layers form a memory cell column. The two doped regions are disposed in the substrate at both sides of the memory cell column.