Abstract: An apparatus for covering a connection port assembly is disposed on a motherboard, and includes a door frame and a shielding plate. The door frame includes two support members, a connecting member, and a latch on the connecting member. A fixed end of each support members is fixed on the motherboard. Connecting ends of the two support members are connected to the connecting member to define an accommodating area for disposing the connection port assembly. The shielding plate includes an upper flange and a plate body. The plate body has one or more opening, an upper edge, and a lower edge. A signal connection surface of the connection port assembly is exposed via the opening. The upper flange is extending from the upper edge and has a latch hole. The latch is engaged into the latch hole to fix the shielding plate to the door frame.

Abstract: A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.

Abstract: A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.

Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

Abstract: A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch.

Abstract: An organic light-emitting device includes a first substrate, a light-emitting structure layer, a first electrode layer, a second electrode layer, a second substrate, first conduction members, a second conduction member and protection structures. The light-emitting structure layer is disposed on the first substrate. The first electrode layer is disposed on the light-emitting structure layer and includes pad-like patterns. The second electrode layer is disposed between the light-emitting structure layer and the first substrate. The second substrate is adhered on the first electrode layer and includes a first circuit and a second circuit. The first circuit includes a continuous pattern and contact portions. The first conduction members are connected between the first circuit and the first electrode layer. The second conduction member is connected between the second circuit and the second electrode layer.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Abstract: A connector cover is adapted to cover a connector and be fixed to a main board. The connector includes a connector top surface having a connector slot, a connector bottom surface and four connector laterals. The connector cover includes a cover top surface, four cover laterals, at least one bending pin and at least one connecting pin. The four cover laterals are adapted to cover the four connector laterals, and two of the cover laterals are connected to the cover top surface. The bending pin extends from the cover lateral and is adapted to be bent to lean against the connector bottom surface. The connecting pin extends from the cover lateral. The connector cover is connected to the main board through the connecting pin. A connector assembly is further provided.

Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.

Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.

Abstract: A light guide bar adapted to be interleaved between two connectors which are disposed on a main board. Each of the connectors has a connector lateral wall. At least one connector includes a positioning protrusion. The light guide bar includes a body. The body includes two opposite light guide bar lateral walls and at least one positioning recess. Each positioning recess is formed on one of the light guide bar lateral walls. The at least one positioning recess is adapted to be positioned on the positioning protrusion of the at least one connector. A connector assembly having the light guide bar and the two connectors is further provided.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues.

Abstract: A single memory cell has the functions of a storage element and a selector. The memory cell includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. The tunneling structure is a stack structure including a first material layer, a second material layer and a third material layer. By adjusting a bias voltage that is applied to the P-type layer and the N-type layer, the tunneling structure is controlled to be in the amorphous state or the crystalline state. Consequently, the memory cell has the memorizing and storing functions. The memory cell has the P-type layer, the tunneling structure and the N-type layer. By adjusting the bias voltage, the function of the selector is achieved.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.