Patents by Inventor Chih-Ming Tzeng
Chih-Ming Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240266985Abstract: A power integrated module (PIM) and a motor control system are provided. The PIM is adapted to drive a motor. The PIM includes a first transformation circuit, a second transformation circuit, and a plurality of shunt units. The first transformation circuit includes a plurality of first half-bridge circuits, and a coupling relationship among the first half-bridge circuits is selected, so that the first transformation circuit is operated in a rectifier mode or an inverter mode. The second transformation circuit includes a plurality of second half-bridge circuits coupled to the motor. The shunt units are respectively coupled between the second half-bridge circuits and the motor and configured to sense a current between the second transformation circuit and the motor.Type: ApplicationFiled: April 26, 2023Publication date: August 8, 2024Applicant: Industrial Technology Research InstituteInventors: Shian-Chiau Chiou, Yu-Hua Cheng, Chih-Ming Tzeng
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Publication number: 20240162114Abstract: A power module including at least one power device, an insulation thermally conductive layer, and a heat dissipation device is provided. The insulation thermally conductive layer has a patterned circuit layer. The power device is disposed on the patterned circuit layer and is electrically connected to the patterned circuit layer. The heat dissipation device includes a heat dissipation plate and a heat dissipation base. The heat dissipation plate has a first surface and a second surface opposite to each other, and the insulation thermally conductive layer is disposed on the first surface. The heat dissipation base is partially bonded to the heat dissipation plate, and a chamber is formed between the heat dissipation plate and the heat dissipation bases. The heat dissipation base has a plurality of first heat dissipation bumps located in the chamber.Type: ApplicationFiled: February 9, 2023Publication date: May 16, 2024Applicant: Industrial Technology Research InstituteInventors: Shian-Chiau Chiou, Chun-Kai Liu, Po-Kai Chiu, Chih-Ming Tzeng, Yao-Shun Chen
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Patent number: 10672677Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.Type: GrantFiled: May 14, 2018Date of Patent: June 2, 2020Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, WIN-HOUSE ELECTRONIC CO., LTD.Inventors: Jing-Yao Chang, Tao-Chih Chang, Kuo-Shu Kao, Fang-Jun Leu, Hsin-Han Lin, Chih-Ming Tzeng, Hsiao-Ming Chang, Chih-Ming Shen
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Patent number: 10288696Abstract: An intelligent diagnosis system for a power module. The system includes a power module, a hardware checking module and a diagnostic module. The power module has a temperature sensing element for obtaining a temperature difference between a starting minimum temperature and a current temperature. The hardware checking module has a current sensing element, a voltage sensing element and a magnetic coupling closed loop detection element for obtaining the current, the output voltage and the input voltage of the power module, and the hardware loop status, respectively. The diagnostic module calculates the number of cycles that have been operated, a measured impedance and an instantaneous power based on those measurement results, and calculating a risk index based on the number of cycles that have been operated, the temperature difference, the measured impedance, the instantaneous power and the hardware loop status, thereby determining the accumulation of the abnormality index record.Type: GrantFiled: November 16, 2016Date of Patent: May 14, 2019Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Chung Chiu, Chih-Ming Tzeng, Li-Ling Liao, Yu-Lin Chao, Chih-Ming Shen, Ming-Kaan Liang, Chun-Kai Liu, Ming-Ji Dai
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Publication number: 20180261519Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.Type: ApplicationFiled: May 14, 2018Publication date: September 13, 2018Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co., Ltd.Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
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Publication number: 20180136287Abstract: An intelligent diagnosis system for a power module. The system includes a power module, a hardware checking module and a diagnostic module. The power module has a temperature sensing element for obtaining a temperature difference between a starting minimum temperature and a current temperature. The hardware checking module has a current sensing element, a voltage sensing element and a magnetic coupling closed loop detection element for obtaining the current, the output voltage and the input voltage of the power module, and the hardware loop status, respectively. The diagnostic module calculates the number of cycles that have been operated, a measured impedance and an instantaneous power based on those measurement results, and calculating a risk index based on the number of cycles that have been operated, the temperature difference, the measured impedance, the instantaneous power and the hardware loop status, thereby determining the accumulation of the abnormality index record.Type: ApplicationFiled: November 16, 2016Publication date: May 17, 2018Inventors: Chih-Chung CHIU, Chih-Ming TZENG, Li-Ling LIAO, Yu-Lin CHAO, Chih-Ming SHEN, Ming-Kaan LIANG, Chun-Kai LIU, Ming-Ji DAI
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Publication number: 20170084521Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.Type: ApplicationFiled: May 4, 2016Publication date: March 23, 2017Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co.,Ltd.Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
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Patent number: 9601474Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: June 15, 2015Date of Patent: March 21, 2017Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20150364457Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: June 15, 2015Publication date: December 17, 2015Applicant: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 9059181Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: November 18, 2013Date of Patent: June 16, 2015Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20140217587Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: November 18, 2013Publication date: August 7, 2014Applicant: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 8587091Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: June 26, 2012Date of Patent: November 19, 2013Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 8314482Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: October 5, 2007Date of Patent: November 20, 2012Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20120267765Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Applicant: Industrial Technology Research InstituteInventors: Shou-Lung CHEN, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 7528009Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: April 19, 2007Date of Patent: May 5, 2009Assignee: Industrial Technology Research InstituteInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20080029870Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: October 5, 2007Publication date: February 7, 2008Applicant: Industrial Technology Research InstituteInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 7294920Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: July 22, 2005Date of Patent: November 13, 2007Assignee: Industrial Technology Research InstituteInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20070197018Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: April 19, 2007Publication date: August 23, 2007Applicant: Industrial Technology Research InstituteInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20060019484Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: July 22, 2005Publication date: January 26, 2006Applicant: Industrial Technology Research InstituteInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu