Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: An information handling system having a reconfigurable cooling fan holder including a plurality of cooling fans of a cooling system operatively coupled to the reconfigurable cooling fan holder, a reconfigurable frame having a plurality of slidingly adjustable walls including a pair of lengthwise slidingly adjustable walls and a widthwise slidingly adjustable wall where the pair of lengthwise slidingly adjustable walls may be expanded or reduced in length by sliding the at least two slide bars nested adjacent to one another forming each lengthwise slidingly adjustable wall to extend or contract each lengthwise slidingly adjustable wall, and the widthwise slidingly adjustable wall may be expanded or reduced in width by sliding the at least two slide bars nested adjacent to one another forming the widthwise slidingly adjustable wall to extend or contract the widthwise slidingly adjustable wall for adjusting the width and length of the reconfigurable cooling fan holder.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A control method is provided and used to place a target object on a test platform in a cabin of a testing device, to sense the temperature of the target object by a temperature response structure, and then to receive temperature signals of the temperature response structure by a controller, where the controller can regulate the pressure inside the cabin to control the air pressure of the cabin, so that the target object can still maintain good heat dissipation under high power consumption.

Abstract: A control method is provided and used to place a target object on a test platform in a cabin of a testing device, to sense the temperature of the target object by a temperature response structure, and then to receive temperature signals of the temperature response structure by a controller, where the controller can regulate the pressure inside the cabin to control the air pressure of the cabin, so that the target object can still maintain good heat dissipation under high power consumption.

Abstract: A wiper blade having a wiper strip, a primary frame and a pair of secondary frames. The primary frame may have a top side and opposite ends, a connection device capable of connecting the wiper blade to a wiper arm disposed on the top side of the primary frame, and a connection structure disposed on each of the opposite ends of the primary frame. Each secondary frame may have a central pivot connection portion and two leg portions extending from the central pivot connection portion, a pivot structure disposed on the central pivot connection portion of the secondary frames. The pivot structure may be a turn-buckle holder comprising two holder halves and a rivet wherein the rivet passes through the two holder halves and holds them together.

Abstract: The present invention discloses 3D shutter glasses and a 3D display system. The 3D shutter glasses comprise a left eye glass and a right eye glass, wherein both the left eye glass and the right eye glass comprise a light transmitting hole array, wherein the left eye glass and the right eye glass alternately control the corresponding light transmitting hole array to be sequentially opened according to a first predetermined time to receive left eye data images and right eye data images, and the first predetermined time is a spacing interval of alternately sending the left eye data images and the right eye data images. With the aforesaid procedure, the present invention is capable of effectively relieving the visual fatigue as watching 3D images.

Abstract: Disclosed are a liquid crystal panel and a display device, which belong to the technical field of display, and solve the technical problem that color washout exists in VA display devices. The liquid crystal panel includes a plurality of sub-pixel units arranged in an array, and each of the sub-pixel units includes at least two sub-pixels. At least one sub-pixel in one sub-pixel unit has a potential the same as that of at least one sub-pixel in an adjacent sub-pixel unit.

Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Abstract: The present disclosure discloses a method for producing a 2D/3D switchable integral imaging liquid crystal cell, and a liquid crystal cell, the method comprising the following steps: 1) coating a UV adhesive layer on a lower substrate; 2) imprinting grooves on the UV adhesive layer by using an array and then UV-curing the UV adhesive layer; 3) coating a lower transparent conductive film on the cured UV adhesive layer, and planarizing the grooves; and 4) forming a liquid crystal cell with the lower substrate and an upper substrate which is coated with an upper transparent conductive film on a lower surface thereof. 2D and 3D displays are switchable in the liquid crystal cell obtained by the method of the present disclosure, thereby achieving comparable displays of 2D and 3D images through simple and convenient operations.

Abstract: The present invention discloses 3D shutter glasses and a 3D display system. The 3D shutter glasses comprise a left eye glass and a right eye glass, wherein both the left eye glass and the right eye glass comprise a light transmitting hole array, wherein the left eye glass and the right eye glass alternately control the corresponding light transmitting hole array to be sequentially opened according to a first predetermined time to receive left eye data images and right eye data images, and the first predetermined time is a spacing interval of alternately sending the left eye data images and the right eye data images. With the aforesaid procedure, the present invention is capable of effectively relieving the visual fatigue as watching 3D images.

Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Abstract: A liquid crystal lens and a liquid crystal display device. The liquid crystal lens includes a first substrate, a second substrate deposed oppositely, and a liquid crystal layer. A metal layer, an insulation layer, and an electrode layer are stacked on the second substrate adjacent to the first substrate. The electrode layer includes multiple electrodes disposed separately. Wherein, among the multiple electrodes disposed separately, a height of the electrode which a maximum voltage is applied on is lower than a height of an adjacent electrode. By the above way, the actual equivalent refractive index neff of the liquid crystal molecules corresponding to the electrode which the maximum voltage is applied on is close to an equivalent refractive index in an ideal condition. As a result, the three-dimensional (3D) crosstalk can be reduced and the 3D display effect can be improved.

Abstract: A general wiper connecting apparatus (1) comprises: a main body (10) formed with a penetrated hole (13) allowing a pivotal shaft (2a?) of a wiper driving arm (2, 2?, 2?) to be received; a head portion (20) formed with a positioning groove (21) at the location connected with the main body (10) for positioning the wiper driving arm (2, 2?, 2?); a tail portion (30) formed with a pair of elastic clamping pieces (31) for latching the wiper driving arm (2, 2?, 2?); and a pair of side boards (40) disposed at two sides of the main body (10), and respectively formed with a through hole (41) corresponding to the penetrated hole (13), and an insertion slit (400) is respectively formed between the pair of side boards (40) and the main body (10) for allowing the wiper driving arm (2, 2?, 2?) to be inserted.

Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.