Abstract: A method and system for inspecting deviation in dynamic characteristics of a feeding system are provided, and the method includes: exciting the feeding system and detecting vibrations of a subcomponent of a component to be inspected of the feeding system to generate a monitoring excitation signal in a monitoring mode; calculating, by a modal analysis method, monitoring eigenvalues and monitoring eigenvectors of the monitoring excitation signal; determining, by a modal verification method, similarity between the monitoring eigenvalues and standard eigenvalues of a digital twin model and similarity between the monitoring eigenvectors and standard eigenvectors of the digital twin model; determining that the dynamic characteristics of the subcomponent are deviated, when the monitoring eigenvalues and monitoring eigenvectors are not similar to the standard eigenvalues and standard eigenvectors. Therefore, the subcomponent whose dynamic characteristics are deviated can be sensed remotely and precisely.

Abstract: An electrostatic discharge (ESD) protection device includes two N-metal oxide semiconductor (NMOS) elements and a doped region. The two NMOS elements are arranged on a P-substrate, and each NMOS element includes a gate, a source, and a drain. The source and the drain are arranged on two opposite sides of the gate. The doped region is implanted into an outer space of the two NMOS surrounding the two NMOS, and a PN junction is formed by the doped region and the P-substrate.

Abstract: A switching power voltage regulator includes a pulse width modulation (PWM) signal generator, an output circuit and a feedback circuit. The PWM signal generator is configured to generate a PWM signal. The feedback circuit is configured to provide a feedback signal to the output circuit according to an output voltage of the output circuit. The output circuit includes an inductor, a plurality of inverters, and a driver. Each of the inverters includes a first transistor and a second transistor. When the inductor needs to be charged, the driver selectively switches one or more corresponding first transistors on according to the feedback signal.

Abstract: A semiconductor device includes a center semiconductor chip with a plurality of die pads, a plurality of lead frames, and a plurality of connecting components. The lead frame encapsulates the center semiconductor chip. Each connecting components establishes an electrical connection between the center semiconductor chip and the lead frame. At least one of the center semiconductor chip, the lead frame, and the connecting component forms an indicator.

Abstract: A semiconductor device includes a center semiconductor chip with a plurality of die pads, a plurality of lead frames, and a plurality of connecting components. The lead frame encapsulates the center semiconductor chip. Each connecting components establishes an electrical connection between the center semiconductor chip and the lead frame. At least one of the center semiconductor chip, the lead frame, and the connecting component forms an indicator.

Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a p+ doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region.

Abstract: An electrostatic discharge (ESD) protection device is formed in an integrated circuit (IC) with a DC-DC converter. The DC-DC converter includes a high-side switch and a low-side switch in series. The ESD protection device includes a first ESD protection component coupled to the high-side switch in parallel and a second ESD protection component coupled to the low-side switch in parallel. When an ESD occurs, the first ESD protection component is turned on before the high-side switch functions and the second ESD protection component is turned on before the low-side switch functions.

Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel.

Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a p+ doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region.

Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel.

Abstract: A switching power voltage regulator includes a pulse width modulation (PWM) signal generator, an output circuit and a feedback circuit. The PWM signal generator is configured to generate a PWM signal. The feedback circuit is configured to provide a feedback signal to the output circuit according to an output voltage of the output circuit. The output circuit includes an inductor, a plurality of inverters, and a driver. Each of the inverters includes a first transistor and a second transistor. When the inductor needs to be charged, the driver selectively switches one or more corresponding first transistors on according to the feedback signal.

Abstract: An electrostatic discharge (ESD) protection device is formed in an integrated circuit (IC) with a DC-DC converter. The DC-DC converter includes a high-side switch and a low-side switch in series. The ESD protection device includes a first ESD protection component coupled to the high-side switch in parallel and a second ESD protection component coupled to the low-side switch in parallel. When an ESD occurs, the first ESD protection component is turned on before the high-side switch functions and the second ESD protection component is turned on before the low-side switch functions.

Abstract: An electrostatic discharge (ESD) protection device includes two N-metal oxide semiconductor (NMOS) elements and a doped region. The two NMOS elements are arranged on a P-substrate, and each NMOS element includes a gate, a source, and a drain. The source and the drain are arranged on two opposite sides of the gate. The doped region is implanted into an outer space of the two NMOS surrounding the two NMOS, and a PN junction is formed by the doped region and the P-substrate.

Abstract: A MOS device includes a semiconductor substrate having a first conductive type, a source region, a gate structure, and a drain region having a second conductive type. The gate structure is formed on the semiconductor substrate and substantially parallel to a first direction. The source region and the drain region are both disposed in the semiconductor substrate, and on two opposite sides of the gate structure. The source region includes at least a source doped region having the second conductive type, and at least a source contact region having the first conductive type, and the source doped region and the source contact region are alternately arranged along the first direction.

Abstract: A MOS device includes a semiconductor substrate having a first conductive type, a source region, a gate structure, and a drain region having a second conductive type. The gate structure is formed on the semiconductor substrate and substantially parallel to a first direction. The source region and the drain region are both disposed in the semiconductor substrate, and on two opposite sides of the gate structure. The source region includes at least a source doped region having the second conductive type, and at least a source contact region having the first conductive type, and the source doped region and the source contact region are alternately arranged along the first direction.

Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.

Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.

Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.

Abstract: A device and a method for testing a switch matrix used in semiconductor equipment and its ring connector are provided by the present invention. The switch matrix contains a test fixture adapter and the ring connector, and the ring connector comprises a plurality of first connecting pins on one end of the ring connector. The method is to first place a probe board on the test fixture adapter, and a plurality of testing pins are positioned on the probe board, each of the testing pins having one corresponding first connecting pin. Then, a resistor is electrically connecting between each of two adjacent testing pins, and electrically connecting the first connecting pins with the corresponding testing pins. Finally, a testing circuit is used to test each of the resistors so as to judge the operations of the switch matrix.