Abstract: A method for improving access performance of a non-volatile storage device when programming data of a size smaller than a fixed minimum program number (FMPN) is disclosed. The method includes the steps of: predetermining a size of a blank data section for combining with a first data section and a second data section, the total size of the first data section, the second data section and the blank data section equals the FMPN; reading out data located at the second data section; updating a new data to the first data section; combining the new data with the data at the second data section; and incorporating the combined data with the blank data of the blank data section to become a final data, and programming the final data.

Abstract: A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix.

Abstract: The present disclosure illustrates a low density parity-check code decoder adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes k calculation units and n shift units, and the memory includes n memory units. The memory is coupled to the calculation module. Each shift unit is one-to-many coupled to the k calculation units. The n memory units are coupled to the n shift units. The calculation module operatively divides the coding data into n first-bit-strings. The ith calculation unit operatively generates a second-bit-string by calculating ith bits of the n first-bit-strings. The jth shift unit operatively generates a third-bit-string upon receiving jth bits of the k second-bit-strings, and shifts the third-bit-string. The memory units are configured for storing the n shifted third-bit-strings respectively.

Abstract: A method and decoder for early terminating decoding processes of serial concatenated coding are disclosed. The method includes the steps of providing a codeword, encoded by a first coding and a second coding sequentially; setting a maximum syndrome weight; decoding the second coding for the codeword by iterative calculations for syndromes; terminating decoding of the second coding if a number of the iterative calculations reaches a preset number or a syndrome weight of one iterative calculation is equal to or smaller than the maximum syndrome weight, otherwise repeating the decoding step and the terminating step; and decoding the first coding for the codeword.

Abstract: The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2m). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2m).

Abstract: A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced.

Abstract: A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.

Abstract: A decoder for A LDPC code and A BCH code and decoding method thereof are provided. The decoder decodes the encoded data based on the LDPC code and decodes the encoded data based on the BCH code simultaneously. Then the decoder outputs decoded data after the decoding procedure has been finished. Additionally, in the decoding procedure for decoding the encoded data based on the BCH code, the decoded result which the encoded data is decoded based on the LDPC code is utilized, so as to increase the processing speed for decoding the encoded data, and enhance the overall decoding performance.

Abstract: The present disclosure illustrates a decoder for min-sum algorithm low density parity-check code. The decoder is adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes a plurality of calculation units, and the memory includes a plurality of memory units. Each calculation unit includes a check node unit, a first message re-constructor and a second message re-constructor. The calculation module divides the coding data into several data groups, and the data group is calculated by each calculation unit. The check node unit generates a stored-form of a calculating result by calculating the respective data group. The calculating result is reconstructed by the first message re-constructor and summed with the following data group. The memory unit stores the respective calculating result generated from the calculation unit.

Abstract: A data format with ECC information for on-the-fly decoding during data transfer and method for forming the data format are disclosed. The method includes the steps of: dividing a parity check matrix having a message segment and a parity segment into a plurality of layers; choosing parity bit nodes in the parity segment of a first layer connected to check nodes; assembling the chosen parity bit nodes as a first parity segment and the rest parity bit nodes as a second parity segment; reallocating the parity check matrix so that the first parity segment is on the head of the message segment and the second parity segment is on the end of the message segment; forming a generating matrix according to the reallocated parity check matrix; and operating a message with the generating matrix to obtain the codeword.

Abstract: An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of XR, XG and XS according to p parallel computations and 2t syndromes; building up FP; building up F?; building up F?; building up matrix of [XSRG F?]; and designing a circuit which fulfills the operation of [XSRG F?].

Abstract: A method for shortening latency of Chien's search and related circuit are disclosed. The method includes the steps of: determining a shifted factor, p; receiving a BCH codeword; computing a syndrome from the BCH codeword; finding an error-location polynomial based on the syndrome; and processing Chien's search for the error-location polynomial to find out roots thereof. p is a number of successive zeroes from the first bit of the BCH codeword, the Chien's search starts iterative calculations by substituting a variable of the error-location polynomial with a nonzero element in Galois Field, GF(2m), and the nonzero element ranges from ?p+1 to ?n, wherein n is a codelength of the BCH codeword and equals 2m?1, and m is a positive integer.

Abstract: The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2m). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2m).

Abstract: A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced.

Abstract: The present disclosure illustrates a decoder for min-sum algorithm low density parity-check code. The decoder is adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes a plurality of calculation units, and the memory includes a plurality of memory units. Each calculation unit includes a check node unit, a first message re-constructor and a second message re-constructor. The calculation module divides the coding data into several data groups, and the data group is calculated by each calculation unit. The check node unit generates a stored-form of a calculating result by calculating the respective data group. The calculating result is reconstructed by the first message re-constructor and summed with the following data group. The memory unit stores the respective calculating result generated from the calculation unit.

Abstract: The present disclosure illustrates a low density parity-check code decoder adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes k calculation units and n shift units, and the memory includes n memory units. The memory is coupled to the calculation module. Each shift unit is one-to-many coupled to the k calculation units. The n memory units are coupled to the n shift units. The calculation module operatively divides the coding data into n first-bit-strings. The k-calculation unit operatively generates a second-bit-string by calculating every k-bit of the first-bit-string. The n-shift unit operatively generates a three-bit-string upon receiving every n-bit of the second-bit-string, and shifts the three-bit-string. The memory units are configured for storing the shifted three-bit-strings corresponding to each shift unit respectively.

Abstract: A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix.

Abstract: An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of XR, XG and XS according to p parallel computations and 2t syndromes; building up FP; building up F?; building up F?; building up matrix of [XSRG F?]; and designing a circuit which fulfills the operation of [XSRG F?].

Abstract: A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.

Abstract: A method for replacing the address of some bad bytes (bad columns) of the data area and the spare area to the good address of bytes (good columns) in non-volatile storage system is disclosed. The steps of the method are: waiting for a command from a host; judging if there is still some data to be processed; if no, go back to the previous step; if yes, go to next step; judging if a bad column is used; if no, process data access and go back to the step of judging if there is still some data to be processed; and if yes, process data accessing as original operation and increase the address by one.