Abstract: Systems and techniques for creating and displaying a circuit design view are described. A hardware description language (HDL) specification and a power intent specification of the circuit design can be analyzed to determine a correspondence between one or more signals in the HDL specification and one or more isolation cells in the power intent specification. The correspondence can be stored in a memory of a computer, and can be used for annotating a visual representation of a signal in a circuit design view based on a corresponding isolation cell. Next, the circuit design view with the annotated visual representation of the signal can be displayed.

Abstract: Systems and techniques for creating and displaying a circuit design view are described. A hardware description language (HDL) specification and a power intent specification of the circuit design can be analyzed to determine a correspondence between one or more signals in the HDL specification and one or more isolation cells in the power intent specification. The correspondence can be stored in a memory of a computer, and can be used for annotating a visual representation of a signal in a circuit design view based on a corresponding isolation cell. Next, the circuit design view with the annotated visual representation of the signal can be displayed.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.

Abstract: Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.

Abstract: Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set and display current operating mode of the IC design to enable the IC design to be debugged under different operating modes.

Abstract: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: The present invention discloses a turbo molecular pump with improved blade structures. The turbo molecular pump comprises a rotor and a stator, wherein the rotor includes five rotor blade assemblies and the stator includes five stator blade assemblies, and wherein the blade number and the blade angle of each rotor blade assembly and stator blade assembly are adjusted to optimization, so as to enhance the pumping speed and the stability of the turbo molecular pump as well as to reduce the difficulty for manufacturing the turbo molecular pump.

Abstract: A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.

Abstract: The present invention discloses a micro turbine which can be a power source of a distributed pneumatic turbine generator and comprises: a first outer casing comprising a gas inlet, a first accommodating space and a first connecting part; a second outer casing comprising a second accommodating space, a second connecting part and a bearing seat, wherein the second outer casing is connected with the first outer casing by the connection between the second connecting part and the first connecting part; a stator being disposed in the first accommodating space; and a rotor being disposed in the second accommodating space and comprising a rotor body and a rotating shaft, wherein one end of the rotating shaft is pivotally coupled to the center of the stator, and another end of the rotating shaft being pivotally coupled to the center of the bearing seat of the second outer casing and extending toward the outside of the second outer casing.

Abstract: The present invention discloses an improved stator structure of a turbo molecular pump and a method for manufacturing the same. The stator comprises a plurality of stator blade assemblies, and each stator blade assembly comprising an inner shroud ring, an outer shroud ring and a plurality of stator blades, wherein the inner shroud ring, the outer shroud ring and the plurality of stator blades are integrated so that the rigidity of the stator is increased and the stator is not easily to be deformed; the method for manufacturing the stator comprises the steps of: laying a raw material on a computer numerical control (CNC) lathe; proceeding an outline treatment to a shape of each stator blade assembly by a turnery process; and shaping the plurality of stator blades of each stator blade assembly with a five-axis processing machine.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.

Abstract: A switch assembly (40) and a portable electronic device (100) are provided. The portable electronic device includes a body section (20), a cover section (10) rotatably connecting to the body section, and the switch assembly. The switch assembly includes a first magnetic component (43), a second magnetic component (45), and a movable magnetic component (47). The first magnetic component is mounted on the cover section. The second magnetic component is mounted on the body section, and attracts to the first magnetic component to maintain the portable electronic device at a closed position. The movable magnetic component is movably mounted on the body section, and repels both to the first and second magnetic. The movable magnetic component provides a repulsive force to repel the cover rotates outwards from the body section, when the magnetic component is driven to move close to the first and second magnetic components.

Abstract: A switch assembly (40) and a portable electronic device (100) are provided. The portable electronic device includes a body section (20), a cover section (10) rotatably connecting to the body section, and the switch assembly. The switch assembly includes a first magnetic component (43), a second magnetic component (45), and a movable magnetic component (47). The first magnetic component is mounted on the cover section. The second magnetic component is mounted on the body section, and attracts to the first magnetic component to maintain the portable electronic device at a closed position. The movable magnetic component is movably mounted on the body section, and repels both to the first and second magnetic. The movable magnetic component provides a repulsive force to repel the cover rotates outwards from the body section, when the magnetic component is driven to move close to the first and second magnetic components.

Abstract: A power-on reset circuit includes a Schmitt trigger circuit, a voltage divider, and a compensate circuit. The Schmitt trigger circuit includes a plurality of MOS devices of a uniform threshold voltage (Vt) for determining a power reset trigger level. The voltage divider is coupled to an input of the Schmitt trigger circuit for tracking the supply signal. The compensate circuit is operative to generate a small reset pulse to compensate for temperature and the supply signal variation effect.

Abstract: A reference voltage generator includes a first current source, an output current mirror, an output device, and a shunt device. The first current source generates a first current and has a first temperature coefficient. The output current mirror mirrors the first current and generates a second current in response to the first current. The output device provides a reference voltage in response to the second current. The shunt device has a second temperature coefficient that is complementary to the first temperature coefficient, and is operatively coupled in parallel with the output device.