Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.

Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

Abstract: Hybrid silicon TFT and oxide TFT structures and methods of formation are described. In an embodiment, a protection layer is formed over a semiconductor oxide channel layer of the oxide TFT to protect the semiconductor oxide channel layer during a cleaning operation of the silicon TFT.

Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

Abstract: A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern.

Abstract: A thin film transistor and a fabricating method thereof are provided. The thin film transistor includes a semiconductor stacked layer, an insulating layer, a gate, a dielectric layer, a source and a drain. The semiconductor stacked layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer disposed on the first metal oxide semiconductor layer. A resistance value of the first metal oxide semiconductor layer is less than a resistance value of the second metal oxide semiconductor layer. The insulating layer is disposed on the semiconductor stacked layer. The gate is disposed on the insulating layer. The dielectric layer covers the gate, wherein the dielectric layer has a plurality of contact openings. The source and the drain are disposed on the dielectric layer, and filled into the contact openings to electrically connect with the semiconductor stacked layer.

Abstract: A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern.

Abstract: A display system includes a first display panel, an extension display panel, and an optical covering layer. The first display panel has a first viewing area and a first peripheral strip adjacent to one side of the first viewing area. The extension display panel at least partially overlaps the image-displaying side of the first display panel and includes an extension viewing area. The extension viewing area at least partially overlaps the first peripheral strip within a projecting region of the first display panel and connects the first viewing area. The optical covering layer covers the image-displaying side of the first viewing area and the image-displaying side of the extension viewing area.

Abstract: An active device and a fabricating method thereof are provided. The active device includes a buffer layer, a channel, a gate, a gate insulation layer, a source and a drain. The buffer layer is disposed on a substrate and has a positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. The gate is disposed above the channel. The gate insulation layer is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected to the channel.

Abstract: A TFT and a fabricating method thereof are provided. The TFT includes an oxide semiconductor layer, a gate insulating layer, a gate, an oxygen-absorbing layer, an insulating layer, and conductive electrodes. The oxide semiconductor layer includes low-oxygen regions and a channel region between the low-oxygen regions. The gate insulating layer is disposed between the oxide semiconductor layer and the gate, and covers the channel region and exposes the low-oxygen regions. The oxygen-absorbing layer having first openings is disposed on the low-oxygen regions each having a first area exposed by the first opening. The insulating layer having second openings covers the oxygen-absorbing layer, the oxide semiconductor layer, and the gate. The low-oxygen region having a second area is exposed by the second opening within the first opening. The second area is smaller than the first area. The conductive electrodes in the second openings are in contact with the low-oxygen regions.

Abstract: A thin film transistor and a fabricating method thereof are provided. The thin film transistor includes a semiconductor stacked layer, an insulating layer, a gate, a dielectric layer, a source and a drain. The semiconductor stacked layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer disposed on the first metal oxide semiconductor layer. A resistance value of the first metal oxide semiconductor layer is less than a resistance value of the second metal oxide semiconductor layer. The insulating layer is disposed on the semiconductor stacked layer. The gate is disposed on the insulating layer. The dielectric layer covers the gate, wherein the dielectric layer has a plurality of contact openings. The source and the drain are disposed on the dielectric layer, and filled into the contact openings to electrically connect with the semiconductor stacked layer.

Abstract: A semiconductor structure and an organic electroluminescence device applying the same are provided. A gate insulating layer covers a gate electrode disposed on a substrate. A channel layer has a channel length L along a channel direction and has a first side and a second side opposite to the first side. The channel layer is located on the gate insulating layer over the gate electrode. A source electrode and a drain electrode are located at and electrically connected to the first side and the second side of the channel layer, respectively. A conductive light-shielding pattern layer is disposed on a dielectric layer covering the source electrode, the drain electrode and the channel layer, and is overlapped to a portion of the source electrode and a portion of the channel layer in a vertical projection. The conductive light-shielding pattern layer and the channel layer have an overlapping length d1, and 0.3?d1/L?0.85.

Abstract: An active device and a fabricating method thereof are provided. The active device includes a buffer layer, a channel, a gate, a gate insulation layer, a source and a drain. The buffer layer is disposed on a substrate and has a positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. The gate is disposed above the channel. The gate insulation layer is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected to the channel.

Abstract: An active device and a fabricating method thereof are provided. The active device includes a buffer layer, a channel, a gate, a gate insulation layer, a source and a drain. The buffer layer is disposed on a substrate and has a positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. The gate is disposed above the channel. The gate insulation layer is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected to the channel.

Abstract: A semiconductor structure and an organic electroluminescence device applying the same are provided. A gate insulating layer covers a gate electrode disposed on a substrate. A channel layer has a channel length L along a channel direction and has a first side and a second side opposite to the first side. The channel layer is located on the gate insulating layer over the gate electrode. A source electrode and a drain electrode are located at and electrically connected to the first side and the second side of the channel layer, respectively. A conductive light-shielding pattern layer is disposed on a dielectric layer covering the source electrode, the drain electrode and the channel layer, and is overlapped to a portion of the source electrode and a portion of the channel layer in a vertical projection. The conductive light-shielding pattern layer and the channel layer have an overlapping length d1, and 0.3?d1/L?0.85.