Patents by Inventor Chih-Pang Liu

Chih-Pang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7286897
    Abstract: The present disclosure provides a system for monitoring semiconductor manufacturing in real time which includes an icon module with a database for storing a plurality of icons to provide stored icons that use vector data to represent respective pieces of equipment employed in semiconductor manufacture, a layout module which includes a database for storing information on a layout of a semiconductor manufacturing facility to provide stored information on the layout, and a joiner module, which is receptive to the icon module and the layout module, for using vector data to merge stored icons received from the icon module with stored information on the layout received from the layout module to produce a merged graphical layout of the semiconductor manufacturing facility. Upon merging, the icons are accessible in the merged graphical display to display real time information relating to semiconductor manufacture.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: October 23, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Pang Liu, Chen-Hsien Ho
  • Publication number: 20060070014
    Abstract: The present disclosure provides a system for monitoring semiconductor manufacturing in real time which includes an icon module with a database for storing a plurality of icons to provide stored icons that use vector data to represent respective pieces of equipment employed in semiconductor manufacture, a layout module which includes a database for storing information on a layout of a semiconductor manufacturing facility to provide stored information on the layout, and a joiner module, which is receptive to the icon module and the layout module, for using vector data to merge stored icons received from the icon module with stored information on the layout received from the layout module to produce a merged graphical layout of the semiconductor manufacturing facility. Upon merging, the icons are accessible in the merged graphical display to display real time information relating to semiconductor manufacture.
    Type: Application
    Filed: September 27, 2004
    Publication date: March 30, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Pang Liu, Chen-Hsien Ho
  • Patent number: 6799909
    Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: October 5, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann
  • Publication number: 20040115842
    Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.
    Type: Application
    Filed: April 4, 2003
    Publication date: June 17, 2004
    Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann
  • Patent number: 6730604
    Abstract: A method for dynamically maintaining compatible contamination levels of equipment, wafer Lots and FOUP's used for automated processing of a Split Lot of wafers. Processing of the test Lot and the production Lot continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold and its designated contamination level is saved until the alternate processing or test Lot processing is completed. The contamination level of the Split Lot is reevaluated based on the completed process(es) and will be designated at the same level it carried at the Split or a higher contamination level if appropriate. The two Lots are then merged and given the highest contamination level of either the saved level or the Split Lot. The two Lots are then processed according to the original predefined process steps and at the redefined contamination level.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: May 4, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Pang Liu, Hao Ming Gong, Hsien Jung Hsu, I-Chun Chen, Tse An Chou, Larry Jann