Abstract: A speed-up hardware architecture used in wireless encryption/decryption operation comprises: a plurality of operation units, that each operation unit is capable of accomplishing a designated operation independently, further comprising: a data receiving device having two inputs that a first input is used for receiving an external data signal and a second input is used for receiving a supporting signal coming from the other operation unit, wherein when an operating mode of the data receiving device is “normal”, the data receiving device will output the first input, and when an operating mode of the data receiving device is “speed-up”, the data receiving device will output the second input; and an operating device coupling to the data receiving device for processing the data from the data receiving device and outputting the processed data thereafter; and a control unit coupling to every operation unit in the architecture for enabling the operation units which are idle to assist the working operation units for da

Abstract: The present invention relates to a programmable data processing apparatus that can minimize the extent of hardware modification by using a storage unit for storing the mutable fields of the WLAN encryption standard, while the encryption standard used in wireless local area network (WLAN) is varied. The programmable data processing apparatus comprises: a first storage unit, which stores at least an auxiliary data, wherein the auxiliary data stored in the first storage unit can be renew from outside when the encryption standard is varied; a reader, coupled to the first storage unit, which is used for receiving an index so as to read a corresponding auxiliary data from the first storage unit; a processor, coupled to the reader, for receiving the auxiliary data and a data signal, wherein, the processor will processes the data signal according to the auxiliary data so as to output a processed signal.

Abstract: A speed-up hardware architecture used in wireless encryption/decryption operation comprises: a plurality of operation units, that each operation unit is capable of accomplishing a designated operation independently, further comprising: a data receiving device having two inputs that a first input is used for receiving an external data signal and a second input is used for receiving a supporting signal coming from the other operation unit, wherein when an operating mode of the data receiving device is “normal”, the data receiving device will output the first input, and when an operating mode of the data receiving device is “speed-up”, the data receiving device will output the second input; and an operating device coupling to the data receiving device for processing the data from the data receiving device and outputting the processed data thereafter; and a control unit coupling to every operation unit in the architecture for enabling the operation units which are idle to assist the working operation units for da

Abstract: An inverse key evaluation circuit for inversely generating a plurality of pre-keys in sequence according to an original key, and a crypto-system containing the inverse key evaluation circuit for decrypting a ciphered text into a plain text according to the plurality of pre-keys. The inverse key evaluation circuit includes a key-receiving module and an inverse key evaluation module. The key-receiving module includes a register for temporally receiving and storing the original key, which will be processed by the inverse key evaluation module to generate the plurality of pre-keys of the original key. The key stored in the register will then be replaced by the newly generated pre-key in sequence. The crypto-system includes a key-generating module that contains the inverse key evaluation circuit, an encryption module, and a decryption module.