Abstract: Semiconductor components and systems having substrate contacting surfaces with a reduced hardness are provided. Systems and components include a ceramic, metallic, or non-metallic component for contacting a substrate. Systems and components include a layer of coating material on at least a portion of a substrate contacting surface of the component. Systems and components include where the component for contacting a substrate includes a component Vickers hardness value, and the layer of coating material exhibits a coating layer Vickers hardness value. Systems and components include where the coating layer Vickers hardness value is greater than or about 10% less than the component Vickers hardness value.

Abstract: A method of updating firmware of a BMC of a server, the server includes the BMC and a PLD, the method includes: in response to receipt of a firmware update instruction to update the firmware of the BMC, the BMC storing in the PLD a firmware configuration file that contains current settings; the BMC updating the firmware after storing the firmware configuration file in the PLD; the BMC being reset after updating the firmware; and the BMC executing an initializing process that includes sub-steps of reading the firmware configuration file from the PLD and applying the current settings contained in the firmware configuration file to the firmware.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: An embodiment of the present disclosure provides a semiconductor device. The semiconductor device has a first semiconductor structure; a second semiconductor structure on the first semiconductor structure and having a first aluminum content; a plurality of voids in the second semiconductor structure; an active structure between the first semiconductor structure and the second semiconductor structure; and a third semiconductor structure between the active structure and the second semiconductor structure, and having a second aluminum content. The first aluminum content is greater than the second aluminum content.

Abstract: A vapor-phase/liquid-phase fluid heat exchange unit includes: a first cover body having a first and a second side, a vapor outlet and a liquid inlet, the vapor outlet and the liquid inlet being in communication with the first and second sides; and a second cover body having a third and a fourth side, the first and second cover bodies being correspondingly mated with each other to together define a heat exchange space. A working fluid and a fluid separation unit are disposed in the heat exchange space. The fluid separation unit partitions the heat exchange space into an evaporation section corresponding to the vapor outlet and a backflow section corresponding to the liquid inlet.

Abstract: Disclosed are an endoscope host and an endoscope device for intelligently detecting organs including a main body having a connection channel for inserting an endoscope tube, and a drive connection part and an electrical connection identification part have first electrical connection points and second electrical connection point respectively. When the endoscope tube is inserted into the connection channel, the endoscope tube is electrically conducted with the first electrical connection point and the second electrical connection point to generate a driving signal and a type signal respectively. An organ identification unit is provided for storing an organ comparison table and comparing the type signal with the organ comparison table to obtain the organ type of the endoscope tube and generate an execution signal. A processing unit is installed in the main body for receiving the driving signal and the type signal and displaying a result image according to the execution signal.

Abstract: A three-phase resonant converter includes a three-phase transformer, an input bridge arm assembly, an output bridge arm assembly, and a control unit. The input bridge arm assembly has three input switch arms, and each input switch arm has an upper switch and a lower switch. The output bridge arm assembly has three output synchronous rectification switch arms respectively coupled to the three secondary-side windings. Each output synchronous rectification switch arm has an upper rectification switch and a lower rectification switch. The control of each output synchronous rectification switch arm is corresponding to the control of each input switch arm. The control unit controls the upper rectification switch or the lower rectification switch to be turned on with a leading phase angle to the corresponding upper switch or the lower switch so as to maintain an output voltage of the resonant converter to be higher than a voltage threshold.

Abstract: A control method applied to a power supply system. The power supply system comprises at least one first power unit and a second power unit, and the at least one first power unit is configured to provide power to an electrical load according to a power provided by a power source. The control method comprises: detecting a load status of the power supply system; when the load status is determined to be a peak load, generating a trigger signal; and in response to the trigger signal, disabling a first-stage converter in the second power unit, and controlling an energy storage capacitor in the second power unit to provide power to the electrical load, wherein the energy storage capacitor is coupled between the first-stage converter and a second-stage converter in the second power unit.

Abstract: An antibody or an antigen-binding portion thereof binding to CHI3L1 includes a heavy chain variable region and a light chain variable region. The antibody or the antigen-binding portion thereof targeting CHI3L1 not just inhibit activated AKT and ERK signals, cancer cells migration, tumor progression, tumor fibrosis, angiogenesis and cancer-induced muscle loss such as cachexia, but modulate TME toward an immunostimulatory phenotype.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first photonic routing structure over a substrate, disposing the first photonic routing structure over a redistribution structure, disposing a second photonic routing structure and an optical engine die on the redistribution structure and forming a molding structure between and separating the first photonic routing structure and the second photonic routing structure.

Abstract: The present disclosure relates to mir-17˜92 as a candidate therapeutic or diagnostic target of motor neuron (MN) degeneration diseases. Expression of mir-17˜92 is sustained throughout adulthood in spinal MNs and specifically decreases before the onset of MN loss in SOD1G93A mice. Accordingly, mir-17˜92 can be used as a candidate therapeutic target for ALS.

Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Abstract: A driving apparatus and an operation method thereof are provided. The driving apparatus includes a first driving circuit and a second driving circuit. The first driving circuit suspends performing at least one of a display driving operation and a touch sensing operation during a skip period under a driving mode, and the first driving circuit performs the at least one of the display driving operation and the touch sensing operation outside the skip period under the driving mode. The second driving circuit is coupled to the first driving circuit. The second driving circuit performs a fingerprint sensing operation during the skip period.

Abstract: A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to 1/4 of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.

Abstract: A display apparatus and an fingerprint sensing method thereof are provided. A display panel of the display apparatus has a pixel circuit array, an in-display touch sensor array, and an in-display fingerprint sensor array. A driving circuit drives the in-display fingerprint sensor array to read a fingerprint image. A current display frame period is divided into a plurality of unit periods, each of the unit periods includes at least one fingerprint sensing period and one or both of a display driving period and a touch sensing period. The driving circuit resets a current fingerprint sensor in the in-display fingerprint sensor array during a first fingerprint sensing period among these fingerprint sensing periods of the first display frame period. The driving circuit reads a sensing result of the current fingerprint sensor during a second fingerprint sensing period succeeding to the first fingerprint sensing period.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure (e.g., an integrated circuit (IC) die) comprising an enhanced cap layer for pad oxidation prevention, as well as a method for forming the IC die. An interconnect pad overlies a substrate at a top of an interconnect structure, and a bond structure overlies and extends from a surface of the interconnect pad. A cap layer and an etch stop layer overlie the surface around the bond structure. Further, the cap layer separates the etch stop layer from the interconnect pad and is soft. Soft may for example, refer to a hardness less than silicon nitride and/or less than the etch stop layer. Because the cap layer is soft, a probe may be pushed through the cap layer to the interconnect pad for testing without first forming a pad opening exposing the interconnect pad.

Abstract: An illumination module includes a light source and a first optical element. The illumination module is set in an optical apparatus. The light source includes a plurality of lighting units and each lighting unit emits a light beam, wherein the light beam includes a colored light and the light source emits a plurality of light beams. The first optical element includes a plurality of optical units.

Abstract: A photo-detecting device includes a first semiconductor layer, a second semiconductor layer located on the first semiconductor layer, a light-absorbing layer located between the first semiconductor layer and the second semiconductor layer, an insulating layer located on the second semiconductor layer, and an electrode structure located on the insulating layer. The second semiconductor layer includes a first region having a first conductivity-type and a second region having a second conductivity-type different from the first conductivity-type. The first region is surrounded by the second region, and includes a geometric center and an interface between the first region and the second region. The insulating layer covers the first region and the second region. The electrode structure includes an outer sidewall located on the second region. In a top view, the interface is located between the geometric center and the outer sidewall.