Patents by Inventor Chih-Peng Fan

Chih-Peng Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230068160
    Abstract: A package carrier including a multi-layer circuit substrate and a silicon wafer is provided. The multi-layer circuit substrate has a first opening and a second opening communicating with each other. A first diameter and a first depth of the first opening are respectively greater than a second diameter and a second depth of the second opening. The silicon wafer is embedded in the first opening of the multi-layer circuit substrate. The silicon wafer has an active surface and includes a connecting circuit layer. The connecting circuit layer is disposed on the active surface and electrically connected to the multi-layer circuit substrate. The second opening of the multi-layer circuit substrate exposes part of the connecting circuit layer.
    Type: Application
    Filed: May 12, 2022
    Publication date: March 2, 2023
    Applicant: Subtron Technology Co., Ltd.
    Inventors: Shaw-Wen Lao, Chih-Peng Fan, Ping-I Cheng
  • Publication number: 20170194721
    Abstract: A novel electrical connector and method of manufacture is disclosed which provides an integral attachment and retention means for the purpose of electrically and mechanically interconnecting circuit elements in electronic devices, said circuit elements including but not limited to printed circuit boards, flexible printed circuits, rigid flex circuits, semiconductor package substrates, modules, and batteries. The electrical connector of the present invention utilizes a bonding material, disposed at least between the electrical spring contact elements on a surface of the connector, to bond and retain first and second portions of the electrical connector in an actuated state on a mating circuit element whereby stable and low resistance electrical interconnections are formed and maintained between the electrical connector and interconnection terminals on the mating circuit element. This design permits the electrical connector to be low-profile and use a reduced amount of space on a circuit member such as a PCB.
    Type: Application
    Filed: January 7, 2017
    Publication date: July 6, 2017
    Inventors: Chih-Peng Fan, Ching-Ho Hsieh, Min-Hsing Wu, David L. Chen, Woody James Maynard
  • Publication number: 20160380372
    Abstract: A novel interconnection structure and method of manufacture is provided which provides an improved means of interconnecting external connector interfaces, such as Universal Serial Bus (USB) connectors, to the internal system boards of electronic devices, such as laptop computers, tablets, and mobile phones. An external connector interface used for interconnecting separate electronic devices is connected to the internal system board of the device in which it resides by being interconnected mechanically and electrically, or alternatively being integral to and of a unitary structure with, a printed circuit substrate, said printed circuit substrate having a plurality of conductive, elastic spring contacts mounted on one surface, with at least one of said electrical spring contacts electrically interconnected to the external electrical connections of the USB connector, and said electrical spring contacts providing an electrical interconnection means to a system board inside the electronic device.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 29, 2016
    Inventors: Ching-Ho Hsieh, Bohdan P. Wozniak, David L. Chen, Chih-Peng Fan, Ming-Hsing Wu
  • Patent number: 9420690
    Abstract: The instant disclosure relates to a connector including a wiring layer, a dielectric layer, a conductive structure, a first protective layer and at least one cantilever structure. The dielectric layer is disposed on the wiring layer, wherein the dielectric layer has at least one via hole to partially expose the wiring layer. The conductive structure is disposed on the inner wall of the at least one via hole of the dielectric layer and electrically connected to the wiring layer. The first protective layer is disposed on the dielectric layer. The cantilever structure is disposed between the first protective layer and the dielectric layer, wherein the at least one cantilever structure is electrically connected to the wiring layer via the conductive structure.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: August 16, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Chih-Peng Fan, Ching-Ho Hsieh, Chung-Chi Huang
  • Patent number: 9370099
    Abstract: The instant disclosure relates to a manufacturing method of connector which comprises the following steps. The first step is to provide a substrate layer and forming a first metal layer on the substrate layer. The next step is to pattern the first metal layer to form a wiring layer. The next step is to form a dielectric layer on the wiring layer, wherein the dielectric layer is formed with at least one via hole to partially expose the wiring layer and a conductive structure arranged on the inner wall of the at least one via hole and electrically connected to the wiring layer. The next step is to form a first protective layer on the dielectric layer and at least one cantilever structure between the first protective layer and the dielectric layer. The last step is to remove the substrate layer.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 14, 2016
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chih-Peng Fan, Ching-Ho Hsieh, Chung-Chi Huang
  • Patent number: 9184520
    Abstract: An electrical connector includes a base and an elastic terminal. The base has a recess. The elastic terminal is connected to the base and extends to the recess. The elastic terminal has a fixed end and a free end, the fixed end is connected to the base, and the free end is located at the recess and is curved. When the contact moves towards the recess, the contact is capable of pushing the contact protrusion to bend towards the bottom of the recess so that the free end leans against the bottom of the recess. The electrical connector may further include a contact protrusion connected to the elastic terminal. When the contact moves towards the recess, the contact is capable of pushing the contact protrusion to make the elastic terminal bend towards the bottom portion of the recess so that the free end leans against the bottom of the recess.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 10, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Chih-Peng Fan, Yin-Hwa Cheng, Ching-Ho Hsieh, Ling-Kai Su, Yung-Hao Hsueh
  • Publication number: 20150289377
    Abstract: The instant disclosure relates to a manufacturing method of connector which comprises the following steps. The first step is to provide a substrate layer and forming a first metal layer on the substrate layer. The next step is to pattern the first metal layer to form a wiring layer. The next step is to form a dielectric layer on the wiring layer, wherein the dielectric layer is formed with at least one via hole to partially expose the wiring layer and a conductive structure arranged on the inner wall of the at least one via hole and electrically connected to the wiring layer. The next step is to form a first protective layer on the dielectric layer and at least one cantilever structure between the first protective layer and the dielectric layer. The last step is to remove the substrate layer.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 8, 2015
    Inventors: CHIH-PENG FAN, CHING-HO HSIEH, CHUNG-CHI HUANG
  • Publication number: 20150289374
    Abstract: The instant disclosure relates to a connector including a wiring layer, a dielectric layer, a conductive structure, a first protective layer and at least one cantilever structure. The dielectric layer is disposed on the wiring layer, wherein the dielectric layer has at least one via hole to partially expose the wiring layer. The conductive structure is disposed on the inner wall of the at least one via hole of the dielectric layer and electrically connected to the wiring layer. The first protective layer is disposed on the dielectric layer. The cantilever structure is disposed between the first protective layer and the dielectric layer, wherein the at least one cantilever structure is electrically connected to the wiring layer via the conductive structure.
    Type: Application
    Filed: May 26, 2015
    Publication date: October 8, 2015
    Inventors: Chih-Peng Fan, Ching-Ho Hsieh, Chung-Chi Huang
  • Publication number: 20140335705
    Abstract: An electrical connector includes a base an elastic terminal and an elastic terminal. The base has a recess. The elastic terminal is connected to the base and extends to the recess. When the contact moves towards the recess, the contact is capable of pushing the contact protrusion to bend towards the bottom of the recess. In addition, the electrical connector may further include a contact protrusion connected to the elastic terminal. When the contact moves towards the recess, the contact is capable of pushing the contact protrusion to make the elastic terminal bend towards the bottom portion of the recess.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 13, 2014
    Inventors: Chih-Peng Fan, Yin-Hwa Cheng, Ching-Ho Hsieh, Ling-Kai Su, Yung-Hao Hsueh
  • Publication number: 20140335706
    Abstract: An electrical connector includes a base and an elastic terminal. The base has a recess. The elastic terminal is connected to the base and extends to the recess. The elastic terminal has a fixed end and a free end, the fixed end is connected to the base, and the free end is located at the recess and is curved. When the contact moves towards the recess, the contact is capable of pushing the contact protrusion to bend towards the bottom of the recess so that the free end leans against the bottom of the recess. The electrical connector may further include a contact protrusion connected to the elastic terminal. When the contact moves towards the recess, the contact is capable of pushing the contact protrusion to make the elastic terminal bend towards the bottom portion of the recess so that the free end leans against the bottom of the recess.
    Type: Application
    Filed: April 16, 2014
    Publication date: November 13, 2014
    Applicant: Unimicron Technology Corp.
    Inventors: Chih-Peng Fan, Yin-Hwa Cheng, Ching-Ho Hsieh, Ling-Kai Su, Yung-Hao Hsueh
  • Publication number: 20130029500
    Abstract: The present invention provides a connector including a substrate, at least a conductive via disposed inside the substrate, a pad disposed on one surface of the substrate and electrically connected to the conductive via, a resilient flange disposed on the pad, and an anisotropic conductive adhesive interposed between the pad and the resilient flange to electrically connect the pad with the resilient flange.
    Type: Application
    Filed: April 19, 2012
    Publication date: January 31, 2013
    Inventors: Chih-Peng Fan, Ling-Kai Su, Yen-Ti Chia
  • Patent number: 8289725
    Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: October 16, 2012
    Assignee: Unimicron Technology Corp.
    Inventor: Chih-Peng Fan
  • Patent number: 8186049
    Abstract: A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: May 29, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Chih-Peng Fan, Yen-Ti Chia
  • Publication number: 20120073867
    Abstract: A circuit structure suitable for being disposed on a carrier board. The circuit structure comprises a first patterned conductive layer, a second patterned conductive layer, and a solder mask. The first patterned conductive layer is disposed on the carrier board. The second patterned conductive layer is disposed on a part of the first patterned conductive layer. A part of the edge of the second patterned conductive layer and a part of the edge of the first patterned conductive layer are substantially coplanar. The patterned solder mask covers a part of the first patterned conductive layer and has at least one opening for exposing the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer.
    Type: Application
    Filed: December 7, 2011
    Publication date: March 29, 2012
    Applicant: Unimicron Technology Corp.
    Inventors: Chih-Peng Fan, Yen-Ti Chia
  • Patent number: 7906200
    Abstract: A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: March 15, 2011
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chih-Peng Fan
  • Publication number: 20100319973
    Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. The first core circuit board has at least one metal layer, and the first core circuit board has at least one first conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the first core circuit board and connected to the metal layer. The second core circuit board has at least one wiring layer, and the second core circuit board has at least one second conductive through hole connected to the wiring layer. The dielectric layer is laminated between the first core circuit board and the second core circuit board.
    Type: Application
    Filed: August 6, 2010
    Publication date: December 23, 2010
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventor: Chih-Peng Fan
  • Publication number: 20100319970
    Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.
    Type: Application
    Filed: August 6, 2010
    Publication date: December 23, 2010
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventor: Chih-Peng Fan
  • Publication number: 20100294553
    Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one embedded capacitor, at least one dielectric layer and at least one wiring layer. The core circuit board has at least one metal layer, and the core circuit board has at least one conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the core circuit board and connected to the metal layer. At least one dielectric layer covers the core circuit board, and the dielectric layer has an embedded hole. At least one wiring layer covers the dielectric layer and connected to the embedded hole.
    Type: Application
    Filed: August 6, 2010
    Publication date: November 25, 2010
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventor: Chih-Peng Fan
  • Publication number: 20100215927
    Abstract: A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure.
    Type: Application
    Filed: April 15, 2009
    Publication date: August 26, 2010
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chih-Peng Fan
  • Patent number: 7700986
    Abstract: A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: April 20, 2010
    Assignee: Unimicron Technology Corp.
    Inventors: Han-Pei Huang, Chih-Peng Fan