Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: Disclosed are an endoscope host and an endoscope device for intelligently detecting organs including a main body having a connection channel for inserting an endoscope tube, and a drive connection part and an electrical connection identification part have first electrical connection points and second electrical connection point respectively. When the endoscope tube is inserted into the connection channel, the endoscope tube is electrically conducted with the first electrical connection point and the second electrical connection point to generate a driving signal and a type signal respectively. An organ identification unit is provided for storing an organ comparison table and comparing the type signal with the organ comparison table to obtain the organ type of the endoscope tube and generate an execution signal. A processing unit is installed in the main body for receiving the driving signal and the type signal and displaying a result image according to the execution signal.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first photonic routing structure over a substrate, disposing the first photonic routing structure over a redistribution structure, disposing a second photonic routing structure and an optical engine die on the redistribution structure and forming a molding structure between and separating the first photonic routing structure and the second photonic routing structure.

Abstract: A package structure and a formation method are provided. The method includes bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The method also includes bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.

Abstract: A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.

Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

Abstract: Disclosed are an endoscope host and an endoscope device for intelligently detecting organs including a main body having a connection channel for inserting an endoscope tube, and a drive connection part and an electrical connection identification part have first electrical connection points and second electrical connection point respectively. When the endoscope tube is inserted into the connection channel, the endoscope tube is electrically conducted with the first electrical connection point and the second electrical connection point to generate a driving signal and a type signal respectively. An organ identification unit is provided for storing an organ comparison table and comparing the type signal with the organ comparison table to obtain the organ type of the endoscope tube and generate an execution signal. A processing unit is installed in the main body for receiving the driving signal and the type signal and displaying a result image according to the execution signal.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

Abstract: An antenna system includes a power divider, a first antenna array, a second antenna array, a third antenna array, a delay device, a first switch element, and a second switch element. The power divider has a first output port, a second output port, and a third output port. The first antenna array is coupled to the first output port. The second antenna array is coupled to the second output port. The third antenna array is coupled to the third output port. The first switch element determines whether to couple the first output port to the delay device according to a first control signal. The second switch element determines whether to couple the third output port to a ground voltage according to a second control signal.

Abstract: An antenna system includes a power divider, a first antenna array, a second antenna array, a third antenna array, a delay device, a first switch element, and a second switch element. The power divider has a first output port, a second output port, and a third output port. The first antenna array is coupled to the first output port. The second antenna array is coupled to the second output port. The third antenna array is coupled to the third output port. The first switch element determines whether to couple the first output port to the delay device according to a first control signal. The second switch element determines whether to couple the third output port to a ground voltage according to a second control signal.

Abstract: A lid-opening apparatus for a dust collector includes a base installed on a lid, a controller connected on the base, a cord defining a first end associated with a conduit and a second end associated with the frame, and a limiting member associated with the cord and between the first end and the second end of the cord. The controller can be rotated to a first position and a second position. While the controller is in the first position, the cord is in a loose condition, a flexible portion of the conduit is stretched, and the lid seals the container. While the controller is in the second position, the cord is in a tight condition, the flexible portion of the conduit shortens, and the lid leaves the container.

Abstract: A lid-opening apparatus for a dust collector includes a base installed on a lid, a controller connected on the base, a cord defining a first end associated with a conduit and a second end associated with the frame, and a limiting member associated with the cord and between the first end and the second end of the cord. The controller can be rotated to a first position and a second position. While the controller is in the first position, the cord is in a loose condition, a flexible portion of the conduit is stretched, and the lid seals the container. While the controller is in the second position, the cord is in a tight condition, the flexible portion of the conduit shortens, and the lid leaves the container.

Abstract: An admixture of hydrated alumina and an organic acid surfactant is calcined in an oxygen-depleted atmosphere, cooled before exposing it to air, comminuted and then centrifuged to produce nanometer-grade superfine &agr;-alumina powder.