Patents by Inventor Chih Pin Chang

Chih Pin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210010996
    Abstract: Embodiments include a device for testing biological specimen. The device can include a receiving mechanism to receive a carrier. The carrier may include a holding area. The device includes a camera to capture a plurality of images of the holding area. A processor in the device may utilize the camera module to: adaptively select, based on the plurality of images of the holding area, an analytical algorithm suitable for a motion property that is characteristic of the biological specimen being tested; and perform a set of analytic processes that corresponds to the selected analytic algorithm on the captured imagery to generate an analytic result associated with the biological specimen.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei CHANG, Chiung-Han WANG
  • Patent number: 10886222
    Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 5, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Kuo-Pin Chang, Chih-Wei Hu
  • Patent number: 10878915
    Abstract: A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Pin Chang, Hsien-Jung Chen, Chien-Hung Liu, Chih-Wei Hung
  • Patent number: 10853525
    Abstract: Systems and methods for a hack-proof security keyboard are described. In some embodiments, a keyboard module may include a first circuit configured to detect activation of a plurality of keys and a second circuit configured to detect activation of a subset of the plurality of keys, where the second circuit overlies the first circuit. In other embodiments, a method may include detecting an electrical signal received from a secondary membrane of a keyboard, where the keyboard includes a primary membrane configured to detect individual activation of any of a plurality of keys, and where the secondary membrane is configured to output the electrical signal in response to concurrent activation of a subset of the plurality of keys. The method may also include performing a selected action in response to the detection.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: December 1, 2020
    Assignee: Dell Products, L.P.
    Inventors: Yong-Teng Lin, Geroncio Ong Tan, Timothy C. Shaw, No-Hua Chuang, Erh-Chieh Chang, Chih-Hao Chen, Wen-Pin Huang
  • Patent number: 10852290
    Abstract: Embodiments disclose a device for testing biological specimen. The device includes a receiving mechanism to receive a carrier. The carrier includes a holding area that carries or has been exposed to the biological specimen. The device includes a camera module arranged to capture imagery of the holding area. The camera module includes an focusing motor operable to adjust a focal point of the camera. The device also includes a processor that is configured to utilize the camera module to determine, based on operations of the focusing motor, a volumetric property of the holding area and perform a set of analytic processes on at least a portion of the captured imagery of the holding area to determine one or more properties of the biological specimen.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Bonraybio Co., Ltd.
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei Chang, Chiung-Han Wang
  • Patent number: 10809794
    Abstract: An example method is provided in according with one implementation of the present disclosure. The method includes identifying an intention of a user of a system in relation to a three-dimensional (3D) virtual object and selecting a 3D navigation mode from a plurality of 3D navigation modes based on the identified user intention. The plurality of 3D navigation modes includes at least a model navigation mode, a simple navigation mode, a driving navigation mode, a reaching navigation mode, and a multi-touch navigation mode. The method further includes transitioning the system to the selected 3D navigation mode.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 20, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chih Pin Hsiao, Gregory William Cook, Jishang Wei, Mithra Vankipuram, Nelson L Chang
  • Publication number: 20200328154
    Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Inventors: Yu-Wei JIANG, Kuo-Pin CHANG, Chih-Wei HU
  • Patent number: 10804414
    Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Patent number: 10677841
    Abstract: A composite product testing system including a main management system, a test equipment and a burn-in apparatus is disclosed. The test equipment and the burn-in apparatus are both arranged in a burn-in chamber of the testing system. First, multiple tested products are respectively inserted in multiple gauges of the burn-in chamber, and a burn-in procedure is activated for providing an aging environment. The main management system controls one of the gauges to connect with the test equipment for the test equipment to perform testing on the tested product upon the connected gauge. After the testing is completed, the main management system then controls the gauge to disconnect from the test equipment and re-connect with the burn-in apparatus, so as to monitor the tested product upon the gauge during the burn-in procedure.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 9, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chien-Chung Chang, Hung-Pin Yu, Yu-Jen Chen, Wen-Jen Lo, Chih-Yen Liu
  • Publication number: 20200161756
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Publication number: 20200105533
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Publication number: 20200090884
    Abstract: An information handling system keyboard includes a backlight that illuminates keys by transmitting light from a light source through a light guide under the keys and reflects the light towards the keys with a reflector disposed under the light guide. Varied thickness of one or more of the light source, light guide and reflector at an intersection of the light source, light guide and reflector improve the efficiency of light transmission to the keys, thus providing for a thinner light guide and/or reduced illumination to have a given key illumination.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Applicant: Dell Products L.P.
    Inventors: Erh-Chieh Chang, Wen-Pin Huang, Chih-Hao Chen, Chih-Ping Chang
  • Patent number: 10593697
    Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 17, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh, Yu-Wei Jiang, Kuo-Pin Chang
  • Patent number: 10587041
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 10, 2020
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Publication number: 20200027750
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Patent number: 10541198
    Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien Lin Chang Chien, Chin-Li Kao, Chang Chi Lee, Chih-Pin Hung
  • Patent number: 10497571
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Publication number: 20190333769
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Application
    Filed: April 27, 2018
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Publication number: 20190318134
    Abstract: Systems and methods for a hack-proof security keyboard are described. In some embodiments, a keyboard module may include a first circuit configured to detect activation of a plurality of keys and a second circuit configured to detect activation of a subset of the plurality of keys, where the second circuit overlies the first circuit. In other embodiments, a method may include detecting an electrical signal received from a secondary membrane of a keyboard, where the keyboard includes a primary membrane configured to detect individual activation of any of a plurality of keys, and where the secondary membrane is configured to output the electrical signal in response to concurrent activation of a subset of the plurality of keys. The method may also include performing a selected action in response to the detection.
    Type: Application
    Filed: April 16, 2018
    Publication date: October 17, 2019
    Applicant: Dell Products, L.P.
    Inventors: Yong-Teng Lin, Geroncio Ong Tan, Timothy C. Shaw, No-Hua Chuang, Erh-Chieh Chang, Chih-Hao Chen, Wen-Pin Huang
  • Publication number: 20190302093
    Abstract: Embodiments disclose a device for testing biological specimen. The device includes a receiving mechanism to receive a carrier. The carrier includes a holding area that carries or has been exposed to the biological specimen. The device includes a camera module arranged to capture imagery of the holding area. The camera module includes an focusing motor operable to adjust a focal point of the camera. The device also includes a processor that is configured to utilize the camera module to determine, based on operations of the focusing motor, a volumetric property of the holding area and perform a set of analytic processes on at least a portion of the captured imagery of the holding area to determine one or more properties of the biological specimen.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei CHANG, Chiung-Han WANG