Patents by Inventor Chih-Pin WANG
Chih-Pin WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112032Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: December 13, 2024Publication date: April 3, 2025Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
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Patent number: 12198910Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: GrantFiled: November 17, 2023Date of Patent: January 14, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Jen Yang, Yi-Zhen Chen, Chih-Pin Wang, Chao-Li Shih, Ching-Hou Su, Cheng-Yi Huang
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Patent number: 12125746Abstract: An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.Type: GrantFiled: May 15, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chiang Chen, Chun-Ting Wu, Ching-Hou Su, Chih-Pin Wang
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Publication number: 20240087861Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
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Patent number: 11854776Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: GrantFiled: July 28, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Jen Yang, Yi-Zhen Chen, Chih-Pin Wang, Chao-Li Shih, Ching-Hou Su, Cheng-Yi Huang
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Publication number: 20230307292Abstract: An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.Type: ApplicationFiled: May 15, 2023Publication date: September 28, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
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Patent number: 11688633Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.Type: GrantFiled: July 16, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chiang Chen, Chun-Ting Wu, Ching-Hou Su, Chih-Pin Wang
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Publication number: 20220367160Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
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Patent number: 11488814Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: GrantFiled: October 8, 2019Date of Patent: November 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Jen Yang, Yi-Zhen Chen, Chih-Pin Wang, Chao-Li Shih, Ching-Hou Su, Cheng-Yi Huang
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Patent number: 11211301Abstract: A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.Type: GrantFiled: February 11, 2020Date of Patent: December 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chunting Wu, Ching-Hou Su, Chih-Pin Wang
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Publication number: 20210343587Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
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Publication number: 20210249321Abstract: A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventors: Chunting WU, Ching-Hou SU, Chih-Pin WANG
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Patent number: 11069562Abstract: A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.Type: GrantFiled: January 15, 2020Date of Patent: July 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chiang Chen, Chun-Ting Wu, Ching-Hou Su, Chih-Pin Wang
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Publication number: 20210217659Abstract: A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.Type: ApplicationFiled: January 15, 2020Publication date: July 15, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
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Publication number: 20200161108Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: October 8, 2019Publication date: May 21, 2020Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
