Patents by Inventor Chih-Ping Antony Fan
Chih-Ping Antony Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11797737Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.Type: GrantFiled: August 12, 2021Date of Patent: October 24, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Michal Jerzy Rewienski, Shan Yuan, Michael Durr, Chih Ping Antony Fan
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Patent number: 11734482Abstract: In one aspect, a transistor-level description of a circuit is accessed, where the circuit includes a plurality of transistors. A transistor-level circuit simulation of the circuit's response to an input stimulus is performed, based on the transistor-level description of the circuit. Activity levels for the transistors in the circuit are determined from the transistor-level circuit simulation. A graphical representation of the circuit is rendered. The graphical representation contains graphical elements that represent components of the circuit, and the graphical elements are visually coded according to the activity levels of the transistors in the corresponding components.Type: GrantFiled: November 9, 2021Date of Patent: August 22, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Aleksandrs Krjukovs, Chih-Ping Antony Fan
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Patent number: 11669667Abstract: Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.Type: GrantFiled: February 19, 2021Date of Patent: June 6, 2023Assignee: Synopsys, Inc.Inventors: Peilin Jiang, Mayukh Bhattacharya, Chih Ping Antony Fan
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Patent number: 11443092Abstract: A method, apparatus, and/or computer program product can perform an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling parameter. The method, apparatus, and/or computer program product can call a defect weight function to return the weight from the defect weight formula. The method, apparatus, and/or computer program product can perform the analog defect simulation on the electronic device. The method, apparatus, and/or computer program product can determine a simulation statistic relating to the analog defect simulation utilizing the weight.Type: GrantFiled: May 11, 2020Date of Patent: September 13, 2022Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Miroslava Tzakova, Chih-Ping Antony Fan
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Publication number: 20210374313Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Applicant: Synopsys, Inc.Inventors: Mayukh BHATTACHARYA, Michal Jerzy REWIENSKI, Shan YUAN, Michael DURR, Chih Ping Antony FAN
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Publication number: 20210350058Abstract: A method, apparatus, and/or computer program product can performing an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling parameter. The method, apparatus, and/or computer program product can call a defect weight function to return the weight from the defect weight formula. The method, apparatus, and/or computer program product can perform the analog defect simulation on the electronic device. The method, apparatus, and/or computer program product can determine a simulation statistic relating to the analog defect simulation utilizing the weight.Type: ApplicationFiled: May 11, 2020Publication date: November 11, 2021Applicant: Synopsys, Inc.Inventors: Mayukh BHATTACHARYA, Miroslava TZAKOVA, Chih-Ping Antony FAN
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Publication number: 20210312113Abstract: In modern VLSI technology, often, stacked arrays of smaller sized MOSFETs are used to achieve the desired width and length of a design MOSFET. In analog defect simulation, each physical transistor can contribute to the circuit's defect universe and this can directly lead to tremendous increase in defect simulation time. Here we propose a method of finding equivalent defects in the context of stacked MOSFET arrays that can lead to significant reduction in defect simulation effort and yet provide accurate defect coverage results.Type: ApplicationFiled: April 2, 2021Publication date: October 7, 2021Applicant: Synopsys, Inc.Inventors: Mayukh BHATTACHARYA, Michal Jerzy Rewienski, Shan Yuan, Michael Durr, Chih Ping Antony Fan
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Publication number: 20210264087Abstract: Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.Type: ApplicationFiled: February 19, 2021Publication date: August 26, 2021Applicant: Synopsys, Inc.Inventors: Peilin Jiang, Mayukh Bhattacharya, Chih Ping Antony Fan
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Patent number: 10409941Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.Type: GrantFiled: October 31, 2013Date of Patent: September 10, 2019Assignee: SYNOPSYS, INC.Inventors: Mayukh Bhattacharya, Chih-Ping Antony Fan, Huiping Huang, Vinay Nulkar, Amelia Huimin Shen
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Publication number: 20150120250Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: Synopsis, Inc.Inventors: Mayukh Bhattacharya, Chih-Ping Antony Fan, Huiping Huang, Vinay Nulkar, Amelia Huimin Shen