Patents by Inventor Chih-Ping Lin

Chih-Ping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967898
    Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hung-Chieh Lin, Yi-Ping Hsieh, Jin-Zhong Huang, Hung-Yu Huang, Chih-Hsien Li, Ciao-Yin Pan
  • Patent number: 11955385
    Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Hsiao Wen Lee
  • Patent number: 11942363
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240079392
    Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung Chang, Jeng-Shien Hsieh, Shih-Ping Lin, Chih-Peng Lin, Chieh-Yen Chen, Chen-Hua Yu
  • Patent number: 11923391
    Abstract: A moiré pattern imaging device includes a light-transmissive film and a light-shielding film. The light-transmissive film includes a plurality of imaging units and a light-incident surface and a light-emergent surface opposite to each other. The plurality of imaging units are disposed on the light-incident surface, the light-emergent surface, or a combination thereof and are arranged in two dimensions to form an imaging unit array. The light-shielding film includes a plurality of light-transmissive regions. The light-transmissive regions are arranged in two dimensions to form a light-transmissive array, and the light-shielding film is overlaid on the light-incident surface or the light-emergent surface. The light-transmissive array corresponds to the imaging unit array. The imaging unit array and the light-transmissive array together form a moiré pattern effect to generate an image magnification effect.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: March 5, 2024
    Assignee: SHAANXI YIXIAN XIER INTELLIGENT OPTOELECTRONICS CO., LTD
    Inventors: Chih-Hsiung Lin, Jung-Ping Liu
  • Patent number: 11923440
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20240029970
    Abstract: A keyboard device includes a substrate, a keycap, a first connection member, and a first elastic arm structure. The substrate has a top surface, and the top surface has an assembling region. The keycap is disposed above the assembling region, and the keycap has a bottom surface facing the assembling region. The first connection member is connected between the keycap and the assembling region, the first connection member includes a first assembly side and a second assembly side opposite to the first assembly side, the first assembly side is pivotally connected to the bottom surface of the keycap, and the second assembly side is pivotally connected to the substrate. The first elastic arm structure includes a connection end and a free end opposite to the connection end, the connection end is connected to the first assembly side, and the free end abuts against the bottom surface of the keycap.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 25, 2024
    Inventors: Shin-Chin Weng, Chih-Ping Lin, Shih-Yu Hsu, Liang-Chun Yeh, Bo-Wei Su
  • Patent number: 11815484
    Abstract: A device for measuring the complex dielectric permittivity of a material under test (MUT) includes an electromagnetic wave generating/receiving unit, a transmission line, a self-referencing waveguide section and a sensing waveguide section. The electromagnetic wave generating/receiving unit is configured to generate an electromagnetic wave signal. The transmission line has a first characteristic impedance and transmits the electromagnetic wave signal. The self-referencing waveguide section has a second characteristic impedance, and includes a front end and a back end, wherein a first reflection signal is sent from the front end. The sensing waveguide section is connected to the back end, and configured to cooperate with the back end to send out remaining subsequent reflection signals, wherein the electromagnetic wave generating/receiving unit receives the first reflection signal and the remaining subsequent reflection signals to measure the complex dielectric permittivity of the MUT.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: November 14, 2023
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chih-Ping Lin, Yin Jeh Ngui
  • Publication number: 20230194455
    Abstract: A device for measuring the complex dielectric permittivity of a material under test (MUT) includes an electromagnetic wave generating/receiving unit, a transmission line, a self-referencing waveguide section and a sensing waveguide section. The electromagnetic wave generating/receiving unit is configured to generate an electromagnetic wave signal. The transmission line has a first characteristic impedance and transmits the electromagnetic wave signal. The self-referencing waveguide section has a second characteristic impedance, and includes a front end and a back end, wherein a first reflection signal is sent from the front end. The sensing waveguide section is connected to the back end, and configured to cooperate with the back end to send out remaining subsequent reflection signals, wherein the electromagnetic wave generating/receiving unit receives the first reflection signal and the remaining subsequent reflection signals to measure the complex dielectric permittivity of the MUT.
    Type: Application
    Filed: May 19, 2022
    Publication date: June 22, 2023
    Applicant: National YANG MING Chiao Tung University
    Inventors: Chih-Ping Lin, Yin Jeh Ngui
  • Key
    Patent number: 11328880
    Abstract: A key includes a substrate, a keycap, a connection component, and protruding structures. The connection component includes a first connection member and a second connection member, and the first connection member and the second connection member are between the substrate and the keycap. The protruding structures are disposed on the upper surface of the first connection member and disposed on the upper surface of the second connection member. When the keycap is pressed to a pressed position, the protruding structures on the first connection member and on the second connection member abut against the bottom surface of the keycap, so that a gap is formed between the keycap and the connection component. Therefore, the bottom surface of the keycap does not contact the upper surface of the first connection member and the upper surface of the second connection member so as to prevent from generating keystroke noises.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 10, 2022
    Assignee: CHICONY ELECTRONICS CO., LTD.
    Inventors: Chih-Ping Lin, Shin-Chin Weng, Shih-Yu Hsu, Chih-Feng Chen
  • KEY
    Publication number: 20220020543
    Abstract: A key includes a substrate, a keycap, a connection component, and protruding structures. The connection component includes a first connection member and a second connection member, and the first connection member and the second connection member are between the substrate and the keycap. The protruding structures are disposed on the upper surface of the first connection member and disposed on the upper surface of the second connection member. When the keycap is pressed to a pressed position, the protruding structures on the first connection member and on the second connection member abut against the bottom surface of the keycap, so that a gap is formed between the keycap and the connection component. Therefore, the bottom surface of the keycap does not contact the upper surface of the first connection member and the upper surface of the second connection member so as to prevent from generating keystroke noises.
    Type: Application
    Filed: March 23, 2021
    Publication date: January 20, 2022
    Inventors: Chih-Ping LIN, Shin-Chin WENG, Shih-Yu HSU, Chih-Feng CHEN
  • Patent number: 10373777
    Abstract: A keyboard includes a base plate, a keycap, and at least one balance assembly. The base plate has a plurality of connecting structures. The keycap is above the base plate. The balance assembly includes a balance bar and two silencing members. The balance bar is between the base plate and the keycap and is engaged with the keycap. The silencing members are connected to the balance bar and engaged with the connecting structures. The balance assembly is configured to guide the keycap to move relative to the base plate. Hardnesses of the base plate and the balance bar are greater than a hardness of the silencing members.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: August 6, 2019
    Assignee: Chicony Electronics Co., Ltd.
    Inventors: Chih-Ping Lin, Kuang-Shen Uang
  • Patent number: 10199029
    Abstract: An earpiece of a headset uses a first signal and a second signal received from an in-ear microphone and an outside microphone, respectively, to enhance microphone signals. The in-ear microphone is positioned at a proximal side of the earpiece with respect to an ear canal of a user, and the outside microphone is positioned at a distal side of the earpiece with respect to the ear canal. A processing unit includes a filter, which digitally filters out in-ear noise from the first signal using the second signal as a reference to produce a de-noised signal to thereby enhance the microphone signals.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: February 5, 2019
    Assignee: MediaTek, Inc.
    Inventors: Chao-Ling Hsu, Yiou-Wen Cheng, Chih-Ping Lin, Chieh-Cheng Cheng
  • Publication number: 20180279035
    Abstract: A portable device and a method for entering a power-saving mode are provided. Audio stream is generated by an audio player, and an audio signal is generated according to the audio stream and then transmitted to an earphone via a cable by a digital-analog converter. At least one electrical characteristic on the cable is sensed to generate at least one sensing signal. The at least one sensing signal is sampled to generate at least one data signal. Whether the earphone is inserted into an ear canal is determined according to the at least one data signal. For determining whether the earphone is inserted into the ear canal, an impedance frequency response related to the earphone is obtained according to the at least one data signal, and whether the earphone is inserted into the ear canal is determined according to a characteristic of peaks of the impedance frequency response.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Jing-Yi HUANG, Kuan-Ta CHEN, Chih-Ping LIN
  • Patent number: 10021642
    Abstract: A timing control method for a user equipment (UE) in a wireless communications system, including: obtaining a starting time of a data transmission period from information of a data transmission timing received from a base station of a wireless network; obtaining a starting time of a current data processing period; and adjusting a data processing timing so that the adjusted starting time of the current data processing period is ahead of the starting time of the data transmission period by a predetermined time.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 10, 2018
    Assignee: MEDIATEK INC.
    Inventors: Hsi-Hsien Chen, Fu-Shing Ju, Chih-Ping Lin, Tsung-Cheng Yang, Tsung-Huan Cheng, Ming-Fong Jhang
  • Patent number: 9998815
    Abstract: A portable device and a method for entering a power-saving mode are provided. An audio signal is transmitted to an earphone via a cable. At least one electrical characteristic on the cable is sensed to generate at least one sensing signal. The at least one sensing signal is sampled to generate at least one data signal. Whether the earphone is in listening position is determined according to the at least one data signal. When it is determined that the earphone is not in listening position, the portable device enters a power-saving mode.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 12, 2018
    Assignee: MEDIATEK INC.
    Inventors: Jing-Yi Huang, Kuan-Ta Chen, Chih-Ping Lin
  • Patent number: 9979831
    Abstract: A method for Cellular Text Telephone Modem (CTM) signal transmission includes: converting a CTM transmitter signal carried in a first sampling rate to generate a transmission signal carried in a second sampling rate, wherein the second sampling rate is different from the first sampling rate; and outputting the transmission signal carried in the second sampling rate to a CTM receiver.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: May 22, 2018
    Assignee: MEDIATEK INC.
    Inventors: Ting-Ni Chen, Fu-Shing Ju, Chih-Ping Lin, Yu-Hsin Chen
  • Publication number: 20170372691
    Abstract: An earpiece of a headset uses a first signal and a second signal received from an in-ear microphone and an outside microphone, respectively, to enhance microphone signals. The in-ear microphone is positioned at a proximal side of the earpiece with respect to an ear canal of a user, and the outside microphone is positioned at a distal side of the earpiece with respect to the ear canal. A processing unit includes a filter, which digitally filters out in-ear noise from the first signal using the second signal as a reference to produce a de-noised signal to thereby enhance the microphone signals.
    Type: Application
    Filed: November 7, 2016
    Publication date: December 28, 2017
    Inventors: Chao-Ling Hsu, Yiou-Wen Cheng, Chih-Ping Lin, Chieh-Cheng Cheng