Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.

Abstract: A self-seeded optical parametric amplifier (OPA) system includes a cavity mirror, a wavelength conversion unit, and a dichroic filter. The cavity mirror is configured to allow high transmission for an input laser beam and high reflection for a feedback beam. The wavelength conversion unit is configured to convert the input laser beam into a signal laser beam and an idler laser beam. The dichroic filter is configured to allow one of the signal laser beam and the idler laser beam to pass through the dichroic filter and reflect the other one onto a feedback path.

Abstract: The linear driving mechanism includes a main body, a linear moving component, a guiding component and a driving component. The main body includes a seat and a moving shaft. The driving component is connected to a rotating shaft of the seat. The moving shaft passes through a driving slot formed on the linear moving component. The guiding component is for guiding a linear movement of the linear moving component. A stroke of the linear moving component of the linear driving mechanism can be changed by approaching or distancing the linear moving component and the seat of the main body to increase or decrease the displacement of the moving shaft located inside the driving slot. Therefore, the linear driving mechanism has not only simple structure but also flexibility in use.

Abstract: The present invention discloses a method of real-time quantification of a target nucleic acid in a sample by constructing a reference table of copy number vs. designated parameter from reference samples which sharing the same nucleic acid sequences with the target nucleic acid. The method includes (a) constructing a reference table of copy number vs. designated parameter from reference samples; (b) amplifying the target nucleic acid; (c) monitoring and detecting the amplification of the target nucleic acid in real-time; (d) analyzing the detected signals to get the designated parameter of the target nucleic acid; and (e) looking up and interpolating to the reference table to get the copy number of the target nucleic acid.

Abstract: The present invention discloses a method of real-time quantification of a target nucleic acid in a sample by constructing a reference table of copy number vs. designated parameter from reference samples which sharing the same nucleic acid sequences with the target nucleic acid. After that, obtain the designated parameter of the target sample and get the copy number by looking up and interpolating to the reference table. The object of the present invention is in particular provide methods for the quantification of the target nucleic acid which the target nucleic acid is quantified independently without comparing it to the standard controls by using a calibration curve. This invention will not only provide a new quantifying method, but will also propose a new standard operational method that eliminates the variations accompanying amplification efficiency, polymerase activity, primer concentrations, and instrument variations.

Abstract: The present invention is related to a portable apparatus for performing uni-directional convective qPCR or qRT-PCR in a mixing reagent containing a target nucleic acid and a fluorescence dye including denaturation, annealing and extension processes. The apparatus includes at least a temperature controlling unit which comprises at least one heat source and one temperature sensor, a circulation-enabling container, a light source, a photo-detector, a filter, a set of optical elements, and a processor.

Abstract: A method for measuring contact resistance of a test key pattern is provided. The test key pattern includes several connecting conductive structures and several contacts. The method includes applying a first bias VD1 between a first measuring leg and a second measuring leg so as to produce a first current ID1, in which the connecting conductive structures and the contacts are chained together in series between the two legs. The first current is measured. The number of the connecting conductive structures and the number of the contacts between the first and second measuring legs are counted, respectively denoted as B and A, so as to set a first equation of VD1/ID1=A·Rc+B·Rs, where Rs and Rc respectively represent a single resistance of the connecting conductive structures and a single resistance of the contacts. A third measuring leg in between the first and second measuring legs.

Abstract: A method of fabricating salicide. A metal layer is formed on a substrate with a polysilicon gate and a source/drain region. A material layer is then formed on the metal layer, wherein the material is selected to produce compressive stress as compressive stress is produced on the substrate and to produce tensile stress as tensile stress is produced in the substrate. The material layer needs to be chosen with the same stress produced by the metal layer. A thermal process is then performed on the substrate to form a silicide on the polysilicon gate and the source/drain region. The material layer and the unreacted metal layer are removed and therefore the salicide process is accomplished.

Abstract: A method of forming a dual alignment photomask. The method includes the steps of depositing a light-blocking layer over a glass plate, and then patterning the light-blocking layer. Next, a switchable mask layer is deposited over the light-blocking layer and the glass plate, after which the switchable mask layer is patterned. Finally, a protective layer is formed over the switchable mask layer, the light-blocking layer and the glass plate. The switchable mask layer can be changed from a light-passing state to a light-blocking state by simply changing the surrounding temperature. Therefore, through proper setting the temperature, the same photomask can be used to form trenches and vias of dual damascene structures. Thus, some mask-making cost can be saved and errors due to mask misalignment can be avoided.

Abstract: A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.

Abstract: A method of fabricating a shallow trench isolation structure includes defining a shallow trench isolation region on a substrate covered by a first oxide layer and a mask layer. Then, covering the inner surface of the shallow trench with a silicon nitride layer. After a thermal treatment, two oxide layers are formed at the two sides of the silicon nitride layer, respectively. Then, another oxide layer is formed to fill the shallow trench. Next, a planarization process is performed until the mask layer is exposed. The mask layer and the first oxide layer and the oxide layer higher than the substrate are removed.

Abstract: A dual damascene process is provided. A dielectric layer is formed on a substrate having a conductive region. The dielectric layer is selectively doped to form a doped region aligned over the conductive region. The doped region, the dielectric layer underlying the doped region, and another part of the undoped dielectric layer are etched until the conductive region is exposed, so that a dual damascene opening exposing the conductive region and a trench are formed, wherein the dual damascene opening comprising a upper trench and a lower via hole. The dual damascene opening and the trench are filled with a conductive layer.

Abstract: A method of fabricating an embedded gate electrode is disclosed.