Patents by Inventor Chih-Rong Chen

Chih-Rong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11803097
    Abstract: A self-seeded optical parametric amplifier (OPA) system includes a cavity mirror, a wavelength conversion unit, and a dichroic filter. The cavity mirror is configured to allow high transmission for an input laser beam and high reflection for a feedback beam. The wavelength conversion unit is configured to convert the input laser beam into a signal laser beam and an idler laser beam. The dichroic filter is configured to allow one of the signal laser beam and the idler laser beam to pass through the dichroic filter and reflect the other one onto a feedback path.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: October 31, 2023
    Assignee: HC PHOTONICS CORP.
    Inventors: Ming-Hsien Chou, Jui-Yu Lai, Chih-Rong Chen
  • Publication number: 20200393026
    Abstract: The linear driving mechanism includes a main body, a linear moving component, a guiding component and a driving component. The main body includes a seat and a moving shaft. The driving component is connected to a rotating shaft of the seat. The moving shaft passes through a driving slot formed on the linear moving component. The guiding component is for guiding a linear movement of the linear moving component. A stroke of the linear moving component of the linear driving mechanism can be changed by approaching or distancing the linear moving component and the seat of the main body to increase or decrease the displacement of the moving shaft located inside the driving slot. Therefore, the linear driving mechanism has not only simple structure but also flexibility in use.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 17, 2020
    Inventors: Wei-Yu Chang, Chih-Rong Chen
  • Patent number: 10510436
    Abstract: The present invention discloses a method of real-time quantification of a target nucleic acid in a sample by constructing a reference table of copy number vs. designated parameter from reference samples which sharing the same nucleic acid sequences with the target nucleic acid. The method includes (a) constructing a reference table of copy number vs. designated parameter from reference samples; (b) amplifying the target nucleic acid; (c) monitoring and detecting the amplification of the target nucleic acid in real-time; (d) analyzing the detected signals to get the designated parameter of the target nucleic acid; and (e) looking up and interpolating to the reference table to get the copy number of the target nucleic acid.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: December 17, 2019
    Assignee: Credo Biomedical Pte Ltd.
    Inventors: Jr. Winston Wong, Stephen Chang-Chi Kao, Ying-Ta Lai, Yih-Jyh Shann, Ming-Fa Chen, Chih-Rong Chen
  • Publication number: 20180011967
    Abstract: The present invention discloses a method of real-time quantification of a target nucleic acid in a sample by constructing a reference table of copy number vs. designated parameter from reference samples which sharing the same nucleic acid sequences with the target nucleic acid. After that, obtain the designated parameter of the target sample and get the copy number by looking up and interpolating to the reference table. The object of the present invention is in particular provide methods for the quantification of the target nucleic acid which the target nucleic acid is quantified independently without comparing it to the standard controls by using a calibration curve. This invention will not only provide a new quantifying method, but will also propose a new standard operational method that eliminates the variations accompanying amplification efficiency, polymerase activity, primer concentrations, and instrument variations.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 11, 2018
    Inventors: Jr Winston WONG, Stephen, Chang-Chi KAO, Ying-Ta Lai, Yih-Jyh Shann, Ming-Fa Chen, Chih-Rong Chen
  • Publication number: 20170282178
    Abstract: The present invention is related to a portable apparatus for performing uni-directional convective qPCR or qRT-PCR in a mixing reagent containing a target nucleic acid and a fluorescence dye including denaturation, annealing and extension processes. The apparatus includes at least a temperature controlling unit which comprises at least one heat source and one temperature sensor, a circulation-enabling container, a light source, a photo-detector, a filter, a set of optical elements, and a processor.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 5, 2017
    Inventors: Jr Winston WONG, Stephen, Chang-Chi KAO, Ying-Ta Lai, Ming-Fa Chen, Chih-Rong Chen
  • Publication number: 20010050563
    Abstract: A method for measuring contact resistance of a test key pattern is provided. The test key pattern includes several connecting conductive structures and several contacts. The method includes applying a first bias VD1 between a first measuring leg and a second measuring leg so as to produce a first current ID1, in which the connecting conductive structures and the contacts are chained together in series between the two legs. The first current is measured. The number of the connecting conductive structures and the number of the contacts between the first and second measuring legs are counted, respectively denoted as B and A, so as to set a first equation of VD1/ID1=A·Rc+B·Rs, where Rs and Rc respectively represent a single resistance of the connecting conductive structures and a single resistance of the contacts. A third measuring leg in between the first and second measuring legs.
    Type: Application
    Filed: April 28, 1999
    Publication date: December 13, 2001
    Inventor: CHIH-RONG CHEN
  • Patent number: 6214709
    Abstract: A method of fabricating salicide. A metal layer is formed on a substrate with a polysilicon gate and a source/drain region. A material layer is then formed on the metal layer, wherein the material is selected to produce compressive stress as compressive stress is produced on the substrate and to produce tensile stress as tensile stress is produced in the substrate. The material layer needs to be chosen with the same stress produced by the metal layer. A thermal process is then performed on the substrate to form a silicide on the polysilicon gate and the source/drain region. The material layer and the unreacted metal layer are removed and therefore the salicide process is accomplished.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: April 10, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Chih-Rong Chen
  • Patent number: 6171732
    Abstract: A method of forming a dual alignment photomask. The method includes the steps of depositing a light-blocking layer over a glass plate, and then patterning the light-blocking layer. Next, a switchable mask layer is deposited over the light-blocking layer and the glass plate, after which the switchable mask layer is patterned. Finally, a protective layer is formed over the switchable mask layer, the light-blocking layer and the glass plate. The switchable mask layer can be changed from a light-passing state to a light-blocking state by simply changing the surrounding temperature. Therefore, through proper setting the temperature, the same photomask can be used to form trenches and vias of dual damascene structures. Thus, some mask-making cost can be saved and errors due to mask misalignment can be avoided.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: January 9, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Rong Chen, Wen-Yuan Huang
  • Patent number: 6156655
    Abstract: A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: December 5, 2000
    Assignees: United Microelectronics Corp., United Semiconductor Corp.
    Inventors: Ming-Ching Huang, Chih-Rong Chen, Kuai-Jung Ho, Wen-Yuan Huang, Chi-Chin Yeh
  • Patent number: 6093618
    Abstract: A method of fabricating a shallow trench isolation structure includes defining a shallow trench isolation region on a substrate covered by a first oxide layer and a mask layer. Then, covering the inner surface of the shallow trench with a silicon nitride layer. After a thermal treatment, two oxide layers are formed at the two sides of the silicon nitride layer, respectively. Then, another oxide layer is formed to fill the shallow trench. Next, a planarization process is performed until the mask layer is exposed. The mask layer and the first oxide layer and the oxide layer higher than the substrate are removed.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: July 25, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Rong Chen, Yunn-Ming Tsou, Yong-Fen Hsieh
  • Patent number: 6080663
    Abstract: A dual damascene process is provided. A dielectric layer is formed on a substrate having a conductive region. The dielectric layer is selectively doped to form a doped region aligned over the conductive region. The doped region, the dielectric layer underlying the doped region, and another part of the undoped dielectric layer are etched until the conductive region is exposed, so that a dual damascene opening exposing the conductive region and a trench are formed, wherein the dual damascene opening comprising a upper trench and a lower via hole. The dual damascene opening and the trench are filled with a conductive layer.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: June 27, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Rong Chen, Wen-Yuan Huang
  • Patent number: 6066532
    Abstract: A method of fabricating an embedded gate electrode is disclosed.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: May 23, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Rong Chen, Chi-Chin Yeh