Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A cantilever force sensor with relatively lower On-Force is disclosed, which comprises a top stack, a bottom stack, and a spacer. The first spacer is configured between the top stack and the bottom stack and configured in a first side of the force sensor. A second side, opposite to the first side, of the top stack, is cantilevered from the bottom stack. When the force sensor is depressed from the top side, the second side of the top stack moves down using the first spacer as a fulcrum. Since the cantilevered side can be easily depressed down so that the On-Force for the force sensor is reduced and hence a force sensor with a relatively higher sensitivity is created.

Abstract: A cantilever force sensor with relatively lower On-Force is disclosed, which comprises a top stack, a bottom stack, and a spacer. The first spacer is configured between the top stack and the bottom stack and configured in a first side of the force sensor. A second side, opposite to the first side, of the top stack, is cantilevered from the bottom stack. When the force sensor is depressed from the top side, the second side of the top stack moves down using the first spacer as a fulcrum. Since the cantilevered side can be easily depressed down so that the On-Force for the force sensor is reduced and hence a force sensor with a relatively higher sensitivity is created.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A cantilever force sensor with relatively lower On-Force is disclosed, which comprises a top stack, a bottom stack, and a spacer. The first spacer is configured between the top stack and the bottom stack and configured in a first side of the force sensor. A second side, opposite to the first side, of the top stack, is cantilevered from the bottom stack. When the force sensor is depressed from the top side, the second side of the top stack moves down using the first spacer as a fulcrum. Since the cantilevered side can be easily depressed down so that the On-Force for the force sensor is reduced and hence a force sensor with a relatively higher sensitivity is created.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A piezosensitive sensor includes a first substrate, a second substrate, a first electrode formed on the first substrate, a second electrode formed on the second substrate, and a sensor array. The sensor array includes a plurality of sensing pixels arranged in rows and columns, each sensing pixel of the plurality of sensing pixels includes a piezosensitive element formed between the first electrode and the second electrode for generating an electrical parameter dependent upon a force applied thereto. A sensing pixel of the plurality of sensing pixels is coupled to an upper sensing pixel, a lower sensing pixel, a left sensing pixel and a right sensing pixel via the first electrode and the second electrode in an up direction, a down direction, a left direction and a right direction, respectively.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A device includes a sensor configured to provide a temperature-sensitive voltage and an oscillator. The sensor includes: a first transistor, being a diode-connected transistor; a second transistor coupled between a source of the first transistor and ground, wherein a gate of the second transistor is controllable by an enable signal; and a current source configured to control the first transistor and comprising a third transistor, a drain of which is directly connected to a drain of the first transistor, the third transistor being a diode-connected transistor. The oscillator includes: a digital delay cell; and an adjustment device configured to, based on the temperature-sensitive voltage, adjust a delay of the digital delay cell. The digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: A force sensing device includes a sensor array, a first substrate, a second substrate and a plurality of electrodes. The first substrate has a sensor region and a side region. The second substrate has a sensor region and a side region. The sensor array is formed above the sensor region of the first substrate. The plurality of electrodes are formed on the sensor region and the side region of the first substrate and below the sensor region and the side region of the second substrate, and coupled to the sensor array. The side region of the first substrate, the side region of the second substrate and the plurality of electrodes on the side region are foldable to a back side of the sensor array.

Abstract: A force sensing device includes a sensor array, a first substrate, a second substrate and a plurality of electrodes. The first substrate has a sensor region and a side region. The second substrate has a sensor region and a side region. The sensor array is formed above the sensor region of the first substrate. The plurality of electrodes are formed on the sensor region and the side region of the first substrate and below the sensor region and the side region of the second substrate, and coupled to the sensor array. The side region of the first substrate, the side region of the second substrate and the plurality of electrodes on the side region are foldable to a back side of the sensor array.

Abstract: A projective capacitive force sensing structure is provided. The projective capacitive force sensing structure includes a first substrate, a first electrode, a first capacitance material layer, a second substrate, a second electrode and a third electrode. The stacking order of the projective capacitive force sensing structure is from the first substrate to the second substrate. The second electrode and the third are respectively below and above the second substrate. A first signal is detected between the first electrode and the second electrode and is collected by the first electrode. A second signal is detected between the second electrode and the third electrode and is collected by the third electrode. A force applied by an object is determined according to the first signal and a location of the object is determined according to the second signal. Both the force applied by an object and the location of the object are acquired.

Abstract: A device includes a sensor configured to provide a temperature-sensitive voltage and an oscillator. The sensor includes: a first transistor, being a diode-connected transistor; a second transistor coupled between a source of the first transistor and ground, wherein a gate of the second transistor is controllable by an enable signal; and a current source configured to control the first transistor and comprising a third transistor, a drain of which is directly connected to a drain of the first transistor, the third transistor being a diode-connected transistor. The oscillator includes: a digital delay cell; and an adjustment device configured to, based on the temperature-sensitive voltage, adjust a delay of the digital delay cell. The digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: A device includes a sensor and an oscillator. The sensor provides a temperature-sensitive voltage. The oscillator includes a digital delay cell and an adjustment device. The adjustment device, based on the temperature-sensitive voltage, adjusts a delay of the digital delay cell, wherein the digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: A fast response force sensor is disclosed. The fast response force sensor comprises a solid-state bonding (SSB) spacer and piezo material therein. The SSB spacer is sandwiched between a top stack and a bottom stack of the force sensor. The SSB spacer maintains a fixed relative position between a top stack and a bottom stack of the force sensor when a fixed force is applied or removed. The SSB spacer is in solid state and shall not be significantly deformed while being depressed by a user, and therefore the response time of an output signal is vastly determined by the properties of the piezo material of the force sensor when a force is applied against the force sensor. Therefore, a fast response force sensor can respond quickly to a force applied against it.

Abstract: A device includes a sensor and an oscillator. The sensor provides a temperature-sensitive voltage. The oscillator includes a digital delay cell and an adjustment device. The adjustment device, based on the temperature-sensitive voltage, adjusts a delay of the digital delay cell, wherein the digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: A force sensor having a noise shielding layer is disclosed. For a first embodiment, a top noise shielding layer is configured on a top surface of a force sensor to screen noise signals which are caused by human body's touch or approaching from top of the force sensor. For a second embodiment, a bottom noise shielding layer is configured on a bottom surface of the force sensor to screen noise signals which are caused by human body's touch or approaching from bottom of the force sensor.

Abstract: A hybrid digital analog key switch is designed to generate both a digital signal and an analog signal (DA) from a single key switch after the key is depressed. A pair of spring metal electrodes are electrically coupled to up and down movement of the key stem, and a force sensor is configured on a bottom side of the key module. Both a digital signal and an analog signal are generated when the key is depressed by a user.