Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.

Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

Abstract: A zeroing structure applicable to an adjustable diplexer includes a substrate, holder, motor, lead screw, displacement plate, stop element and interference element. The holder is disposed on the substrate. The motor is disposed on the holder. The lead screw is rotatably disposed on the holder and connected to the motor, and thus rotation of the lead screw is driven by the motor. The displacement plate is movably disposed on the substrate and helically connected to the lead screw so as to undergo linear motion between a first position and a second position relative to the substrate when guided and driven by the motor. The stop element is disposed on the lead screw. The interference element is disposed on the displacement plate and at the position that allows the interference element to come into contact with the stop element when the displacement plate is at the first position.

Abstract: Disclosed herein is a method of producing a polyaniline zirconia nanocomposite, and the uses of the thus produced polyaniline zirconia nanocomposite for the treatment of wastewater. The polyaniline zirconia nanocomposite is characterized in having a particle size of about 0.3 to 50 ?m in diameter, an isoelectric point at about pH 6.2, and is capable of reducing at least 99% of the pathological microorganism and at least 60% of the phosphate in the wastewater after coming into contact with wastewater for 24 hrs and 12 hrs, respectively.

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract: Disclosed herein is a method of producing a polyanilne zircornia nanocomposite, and the uses of the thus produced polyanilne zircornia nanocomposite for the treatment of wastewater. The polyanilne zircornia nanocomposite is characterized in having a particle size of about 0.3 to 50 ?m in diameter; an isoelectric point at about pH 6.2, and is capable of reducing at least 99% of the pathological microorganism and at least 60% of the phosphate in the wastewater after coming into contact with wastewater for 24 hrs and 12 hrs, respectively.

Abstract: An embodiment is a method for providing an adjusted electronic representation of an integrated circuit layout, the method including using one or more processor, generating a timing performance of a path in a first netlist, identifying a first cell in the path that violates a timing performance parameter, and generating a plurality of derivative cells from a subsequent cell that is in the path after the first cell, where each derivative cell includes a variation of the subsequent cell. The method further includes in response to the identifying the first cell, replacing the subsequent cell with at least one of the plurality of derivative cells to generate a first modified netlist, where the variation of the at least one of the plurality of derivative cells reduces the violation of the timing performance parameter, and generating a final netlist based on the first modified netlist.

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract: An I/O pad structure in an integrated circuit (IC) comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.

Abstract: A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Abstract: Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.

Abstract: A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Abstract: A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract: Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.

Abstract: A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

Abstract: This invention discloses an I/O pad structure in an integrated circuit (IC) which comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.

Abstract: A foldable electronic alarm device including a first housing, a second housing, a pivot, a display screen and an alarm module is provided, wherein the pivot is disposed in one side of the first housing and the second housing to enable the first housing to pivot relative to the second housing. The display screen is disposed inside the first housing. Moreover, the alarm module is disposed between the display screen and the first housing. When the alarm module is pressed by the first housing or the display screen, an alarm is sent out by the alarm module.

Abstract: A docking station including a housing, a linkage, a forcing member and a first connector for electrically connecting to a first connector of an electronic device, is provided. The housing includes a platform having a first opening and the electronic device is suitable for being placed on the platform. The housing further comprises a second opening located outside the platform. The linkage is disposed within the housing. The forcing member disposed on the second opening is connected to one end of the linkage, wherein the forcing member is suitable for moving back and forth along a predetermined path to actuate the linkage. The first connector disposed on the first opening is connected to the other end of the linkage, wherein the first connector is suitable for expanding and contracting in the first opening through the linkage to be connected to or disconnected from the second connector of the electronic device.

Abstract: A portable electronic apparatus including a base, a screen and a withdrawer is provided. The screen is pivotally connected to the base and the withdrawer is adopted for assembling to the base. The withdrawer includes a case, a combination lock and a push rod. The case, on which the combination lock is disposed, has an opening for exposing a part of the combination lock. The push rod disposed on the case has a first and a second end, wherein the second end is connected with the combination lock. When the combination lock is locked, the first end of the push rod penetrates through the base so as to fix the relative position between the case and the base; and when the combination lock is unlocked, the first end of the push rod can be withdrawn back into the case to separate the case from the base.