Patents by Inventor Chih Sieh Teng
Chih Sieh Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120273880Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 ?m deep into the body material but not more than 0.1 ?m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.Type: ApplicationFiled: October 26, 2010Publication date: November 1, 2012Inventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
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Publication number: 20120181620Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 ?m deep into the body material but not more than 0.1 ?m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.Type: ApplicationFiled: July 9, 2010Publication date: July 19, 2012Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala, Chih Sieh Teng, Chin-Miin Shyu
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Publication number: 20120181614Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 ?m deep into the body material but not more than 0.1 ?m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.Type: ApplicationFiled: December 1, 2011Publication date: July 19, 2012Inventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
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Patent number: 7879669Abstract: At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 ?m greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 ?m greater than LC.Type: GrantFiled: September 25, 2006Date of Patent: February 1, 2011Assignee: National Semiconductor CorporationInventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
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Patent number: 7145191Abstract: The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion.Type: GrantFiled: August 18, 2004Date of Patent: December 5, 2006Assignee: National Semiconductor CorporationInventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
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Patent number: 6797576Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.Type: GrantFiled: December 20, 2002Date of Patent: September 28, 2004Assignee: National Semiconductor CorporationInventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
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Patent number: 6146958Abstract: Disclosed are methods of making inductors and capacitors, comprising filling a via in a dielectric disposed between two metal layers with a metal plug. The plug comprises tungsten, aluminum or copper and extends the length of the metal layers. The plug connects the two metal layers to form the inductor. Two plugs can be formed so as to connect the two metal layers so as to form a parallel plate capacitor.Type: GrantFiled: September 22, 1998Date of Patent: November 14, 2000Assignee: National Semiconductor CorporationInventors: Ji Zhao, Chih Sieh Teng
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Patent number: 5943564Abstract: A fully complementary double-poly BiCMOS process utilizes substantially identical device architectures to form n-channel and p-channel MOS transistors, as well as npn and pnp bipolar transistors. In the double-poly process, the first layer of polysilicon is utilized to form the source and drain of the MOS transistors as well as the base and collector of the bipolar transistors. The second layer of polysilicon is then utilized to form the gate of the MOS transistors as well as the emitter of the bipolar transistors.Type: GrantFiled: February 13, 1996Date of Patent: August 24, 1999Assignee: National Semiconductor CorporationInventors: Hung-Sheng Chen, Chih Sieh Teng
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Patent number: 5908311Abstract: A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow. The FLASH EPROM cells are formed as single-transistor memory cells that operate on low to very-low voltages.Type: GrantFiled: July 25, 1996Date of Patent: June 1, 1999Assignee: National Semiconductor CorporationInventors: Min-hwa Chi, Chih-sieh Teng, Albert Bergemont
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Patent number: 5899723Abstract: In fabricating a bipolar transistor, semiconductor dopant is introduced into a semiconductor body during a base doping operation to define a doped region, that forms a PN junction with adjoining semiconductor material and abuts a slanted sidewall of a field insulating region. The doped region constitutes a base region for the transistor. The base doping operation entails ion implanting the dopant into the body at a tilt angle of at least 15.degree. relative to the vertical. The minimum lateral base thickness and, the minimum sidewall base thickness increase relative to the minimum vertical base thickness. As a result, the magnitude of the collector-to-emitter breakdown voltage typically increases. The minimum lateral, sidewall, and vertical base thicknesses vary with the tilt angle and base-implant energy in such a manner that the minimum lateral base thickness and the minimum sidewall base thickness are separately controllable from the minimum vertical base thickness.Type: GrantFiled: February 21, 1997Date of Patent: May 4, 1999Assignee: National Semiconductor CorporationInventors: Hung-Sheng Chen, Chih Sieh Teng
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Patent number: 5861647Abstract: Disclosed are methods of making inductors and capacitors, comprising filling a via in a dielectric disposed between two metal layers with a metal plug. The plug comprises tungsten, aluminum or copper and extends the length of the metal layers. The plug connects the two metal layers to form the inductor. Two plugs can be formed so as to connect the two metal layers so as to form a parallel plate capacitor.Type: GrantFiled: October 2, 1996Date of Patent: January 19, 1999Assignee: National Semiconductor CorporationInventors: Ji Zhao, Chih Sieh Teng
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Patent number: 5761126Abstract: The layout and the programming voltage of a single-poly EPROM cell are reduced by eliminating the n+ contact region which is conventionally utilized to place a positive voltage on the n-well of the cell, and by utilizing a negative voltage to program the cell. The negative voltage is applied to a p+ contact region formed in the n-well which injects electrons directly onto the floating gate of the cell.Type: GrantFiled: February 7, 1997Date of Patent: June 2, 1998Assignee: National Semiconductor CorporationInventors: Min-hwa Chi, Chih Sieh Teng, Albert Bergemont
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Patent number: 5733813Abstract: Planarized field isolation regions are formed in a semiconductor substrate to isolate adjacent semiconductor devices by implanting an isolation material, such as oxygen or nitrogen ions, into a substrate patterned to define the field isolation regions. The implanted isolation material combines with the silicon in the substrate to form a field isolation region that extends downward from the surface of the substrate.Type: GrantFiled: May 9, 1996Date of Patent: March 31, 1998Assignee: National Semiconductor CorporationInventors: Hung Sheng Chen, Chih Sieh Teng
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Patent number: 5726069Abstract: A bipolar transistor is fabricated by a process in which first and second dopants of the same conductivity type are introduced into a semiconductor body through at least partially overlapping sections, preferably the same section, of the body's upper surface to form an emitter. The first dopant is introduced at a greater dosage than the second dopant such that the emitter consists at least of a main emitter region constituted primarily with the first dopant. The introduction of the second dopant into the body entails ion implanting the second dopant at a tilt angle of at least 15.degree. relative to a direction generally perpendicular to the body's upper surface. Part of the second dopant is so implanted into an extension zone that extends laterally beyond the main emitter region. The extension zone may be of the same conductivity type as, or of opposite conductivity type to, the main emitter region.Type: GrantFiled: December 2, 1994Date of Patent: March 10, 1998Assignee: National Semiconductor CorporationInventors: Hung-Sheng Chen, Chih Sieh Teng
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Patent number: 5399513Abstract: The present process comprises the use of a differential oxidation of the source/drain regions to permit elimination of the p+ implant mask normally required for formation of p-channel device in a CMOS process. A DDD procedure provides protection against hot-electron effects. A second oxide spacer is included to allow formation of salicide at the contacts to provide low sheet resistance.Type: GrantFiled: November 17, 1992Date of Patent: March 21, 1995Assignee: National Semiconductor CorporationInventors: Tian-I Liou, Chih-Sieh Teng
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Patent number: 4956311Abstract: The present process comprises the use of a blanket phosphorus (n-) implant coupled with a masked boron (P+) implant to permit the elimination of the conventional N+ implant and the LDD masks. The use of the blanket n- implant and the masked p+ implant allows production of an n- drain region which reduces hot-electron-induced degradation and a low concentration S/D region which is subsequently more easily counterdoped by a high concentration implant. A shallow blanket n+ implant is included prior to the P+ mask step to prevent contact resistance problems. Thereafter in the process of this invention, a salicide is formed at the sources and drains to produce a low sheet resistance in the contacts of the n-channel devices, notwithstanding the absence of the conventional thick n+ layer.Type: GrantFiled: June 27, 1989Date of Patent: September 11, 1990Assignee: National Semiconductor CorporationInventors: Tian-I Liou, Chih-Sieh Teng
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Method of forming an N+ poly-to- N+ silicon capacitor structure utilizing a deep phosphorous implant
Patent number: 4877751Abstract: An N+ poly-to-N+ silicon capacitor structure is provided by adding a single mask step to a standard CMOS process flow. The capacitor oxide between the N+ poly plate and the N+ silicon plate is grown simultaneously with gate oxide for the MOSFET devices. A high dose, deep phosphorous implant is employed to form the N+ substrate plate. This results in an excellent capacitance voltage coefficient. The resulting thin interplate oxide leads to high capacitance per unit area and, thus, small die size.Type: GrantFiled: March 11, 1988Date of Patent: October 31, 1989Assignee: National Semiconductor CorporationInventors: Chih-Sieh Teng, Tian-I Liou, Hiekyung Chun-Min