Patents by Inventor Chih-Sien Yeh

Chih-Sien Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip scale package and manufacturing method thereof
    Publication number: 20020127779
    Abstract: A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball.
    Type: Application
    Filed: March 9, 2001
    Publication date: September 12, 2002
    Inventors: Ching-Huei Su, Chih-Chang Yang, Shyh-Wei Wang, Chih-Sien Yeh
  • Chip scale package and manufacturing method thereof
    Patent number: 6221697
    Abstract: A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: April 24, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ching-Huei Su, Chih-Chang Yang, Shyh-Wei Wang, Chih-Sien Yeh