Abstract: An integration of components of SCSI and Ethernet adapter boards onto a single chip forming an integrated Ethernet-SCSI controller for use on a PCI Local Bus. Integration is enabled by a reduction of noise. Noise is first reduced by reducing ground bounce by providing additional VSS pins for supporting large PCI and SCSI output buffers which constantly switch current. The VSS pins supporting the large PCI and SCSI output buffers support a limited number of output buffers located in a local area of the pin as connected to the pin by individual lines. Noise is additionally reduced by providing circuitry on the digital output buffers to limit the change of current over time (di/dt) during switching of the output buffers. Noise is further reduced by locating digital control circuitry so that current density increases in a direction away from analog circuitry.

Abstract: A system upgrade method provides for the integrating of bus master ownership of a single local bus load (e.g., a PCI load) by plural data transceivers. A family of integrated circuits is manufactured to a include an upgrade member having: (a) a first plurality of local bus interface terminals for connecting to a local bus (e.g., PCI); (b) a second plurality of interface terminals for connecting to a first external communications channel (e.g,, SCSI); (c) a third plurality of interface terminals for connecting to a second external communications channel (e.g.

Abstract: An integrated circuit is provided with: (a) a first plurality of local bus interface terminals for connecting to a local bus (e.g., PCI); (b) a second plurality of interface terminals for connecting to a first external communications channel (e.g., SCSI); (c) a third plurality of interface terminals for connecting to a second external communications channel (e.g., Ethernet); (d) a local bus interface means, connected to the first plurality of local bus interface terminals, for interfacing with the corresponding local bus and thereby applying a predefined load to the local bus; (e) a signal multiplexing means, operatively coupled to the local bus interface means, to the first communications channel (SCSI), and to the second communications channel (Ethernet), for selectively routing signals between the local bus interface means and a selected one of the first and second external communications channels (e.g.

Abstract: A glitch filter for eliminating noise pulses less than 12 nanoseconds (ns) created by large devices on the SCSI bus and reflections of the 12 ns pulses created by a long SCSI bus cable, as well as noise pulses on the order of 35 ns typically found on a SCSI bus. The glitch filter includes a Schmitt trigger connected to receive the SCSI bus signal along with three filters connected in series with the Schmitt trigger. The first filter removes positive pulses having a pulse width less than 12 ns and provides an inverted output. The second filter removes negative pulses having a pulse width less than 12 ns and provides an inverted output. The third filter removes pulses having a pulse width less than 35 ns and provides the output of the glitch filter.

Abstract: An interface circuit is provided for connecting to a multi-mode signal bus. The signal bus (e.g., a PCI local bus) can operate in either a first or second signaling mode. The first signaling mode is one in which discrete logic levels (e.g., binary "0" and "1") are represented by a first set of voltage levels (e.g., 0V-5V). The second signaling mode is one in which discrete logic levels are represented by a different, second set of voltage levels (e.g., 0V-3.3V). The interface circuit includes an intermediate level generator circuit for generating, from the first voltage level (5V), an intermediate voltage level (V4) between the possible voltage levels of the first and second signaling modes (V5 and V3). A comparator compares the power level of the signal bus against the intermediate voltage level (V4) and determines which signaling mode the signal bus is operating in. Configurable I/O cells of the interface circuit are then automatically configured to operate in the corresponding signaling mode (V5 or V3).