Patents by Inventor Chih-Ta Wu
Chih-Ta Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20240067512Abstract: An automatic fluid replacement device is adapted to be mounted on an opening of a storage barrel. The automatic fluid replacement device includes a robotic arm, at least one fluid convey joint and a controller. The robotic arm has a gripper. The fluid convey joint includes a convey pipe, a sleeve and a sealing bag. The convey pipe is configured to deliver a fluid. The sleeve is sleeved on the convey pipe. The gripper clamps the sleeve. The sealing bag is sleeved on the sleeve. The controller is configured for automatically controlling the robotic arm to move the fluid convey joint into the opening and controlling the sealing bag to be inflated to seal the opening.Type: ApplicationFiled: October 27, 2022Publication date: February 29, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Cheng-Han TSAI, Wei-Lung PAN, Chih-Ta WU, I-hsin LIN
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Patent number: 11119001Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.Type: GrantFiled: March 5, 2020Date of Patent: September 14, 2021Assignees: NATIONAL CHUNG CHENG UNIVERSITY, TONGTAI MACHINE & TOOL CO., LTD.Inventors: Chih-Chun Cheng, Yu-Sheng Chiu, Wen-Nan Cheng, Ping-Chun Tsai, Yu-Hsin Kuo, Wei-Jen Chen, De-Shin Liu, Chen-Wei Chuang, Chih-Ta Wu, Wen-Peng Tseng, Wen-Chieh Kuo
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Publication number: 20210123830Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.Type: ApplicationFiled: March 5, 2020Publication date: April 29, 2021Inventors: CHIH-CHUN CHENG, YU-SHENG CHIU, WEN-NAN CHENG, PING-CHUN TSAI, YU-HSIN KUO, WEI-JEN CHEN, DE-SHIN LIU, CHEN-WEI CHUANG, CHIH-TA WU, WEN-PENG TSENG, WEN-CHIEH KUO
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Patent number: 9418999Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.Type: GrantFiled: October 28, 2014Date of Patent: August 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ta Wu, Jason Lee, Chung Chien Wang, Hsing-Lien Lin, Yu-Jen Wang, Yeur-Luen Tu, Chern-Yow Hsu, Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai
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Publication number: 20150041874Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Chih-Ta Wu, Jason Lee, Chung Chien Wang, Hsing-Lien Lin, Yu-Jen Wang, Yeur-Luen Tu, Chern-Yow Hsu, Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai
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Patent number: 8889507Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.Type: GrantFiled: June 20, 2007Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ta Wu, Jason Lee, Chung Chien Wang, Hsing-Lien Lin, Yu-Jen Wang, Yeur-Luen Tu, Chern-Yow Hsu, Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai, Lucy Chang, Chia-Lin Chen, Ming-Chih Tsai
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Patent number: 7851324Abstract: A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.Type: GrantFiled: October 26, 2006Date of Patent: December 14, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Chia-Shiung Tsai, Yeur-Luen Tu, Lan-Lin Chao, Chih-Ta Wu, Hsing-Lien Lin, Chung Chien Wang
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Patent number: 7786552Abstract: A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.Type: GrantFiled: June 10, 2005Date of Patent: August 31, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsun Huang, Kuo-Yin Lin, Chung-Yi Yu, Chih-Ta Wu, Chia-Shiung Tsai
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Patent number: 7622347Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.Type: GrantFiled: January 12, 2007Date of Patent: November 24, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hsiung Chiang, Chih-Ta Wu, Tsung-Hsun Huang
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Patent number: 7554145Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.Type: GrantFiled: December 14, 2006Date of Patent: June 30, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Hung Liu, Chih-Ta Wu, Lan-Lin Chao, Yeur-Luen Tu, Wen-Chin Lin, Chia-Shiung Tsai
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Publication number: 20080318378Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.Type: ApplicationFiled: June 20, 2007Publication date: December 25, 2008Inventors: Chih-Ta Wu, Jason Lee, Chung Chien Wang, Hsing-Lien Lin, Yu-Jen Wang, Yeur-Luen Tu, Chern-Yow Hsu, Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai, Lucy Chang, Chia-Lin Chen, Ming-Chih Tsai
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Patent number: 7443005Abstract: An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.Type: GrantFiled: November 5, 2004Date of Patent: October 28, 2008Assignee: Tiawan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Sen Kuo, Feng-Jia Shiu, Gwo-Yuh Shiau, Jieh-Jang Chen, Shih-Chi Fu, Chien Hsien Tseng, Chia-Shiung Tsai, Yuan-Hung Liu, Yeur-Luen Tu, Chih-Ta Wu, Chi-Hsin Lo
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Publication number: 20080188055Abstract: A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.Type: ApplicationFiled: October 26, 2006Publication date: August 7, 2008Inventors: Yu-Jen Wang, Chia-Shiung Tsai, Yeur-Luen Tu, Lan-Lin Chao, Chih-Ta Wu, Hsing-Lien Lin, Chung Chien Wang
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Publication number: 20070111438Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.Type: ApplicationFiled: January 12, 2007Publication date: May 17, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min-Hsiung Chiang, Chih-Ta Wu, Tsung-Hsun Huang
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Publication number: 20070096230Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.Type: ApplicationFiled: December 14, 2006Publication date: May 3, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Hung Liu, Chih-Ta Wu, Lan-Lin Chao, Yeur-Luen Tu, Wen-Chin Lin, Chia-Shiung Tsai
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Patent number: 7202130Abstract: A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.Type: GrantFiled: February 10, 2004Date of Patent: April 10, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Hung Liu, Chih-Ta Wu, Yeur-Luen Tu, Chi-Hsin Lo, Chia-Shiung Tsai
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Patent number: 7199001Abstract: A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.Type: GrantFiled: March 29, 2004Date of Patent: April 3, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ta Wu, Kuo-Yin Lin, Tsung-Hsun Huang, Chung-Yi Yu, Lan-Lin Chao, Yeur-Luen Tu, Hsing-Lien Lin, Chia-Shiung Tsai
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Patent number: 7180116Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.Type: GrantFiled: June 4, 2004Date of Patent: February 20, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hsiung Chiang, Chih-Ta Wu, Tsung-Hsun Huang
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Patent number: 7172908Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.Type: GrantFiled: February 15, 2005Date of Patent: February 6, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Hung Liu, Chih-Ta Wu, Lan-Lin Chao, Yeur-Luen Tu, Wen-Chin Lin, Chia-Shiung Tsai