Patents by Inventor Chih-tang Peng

Chih-tang Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10727064
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Patent number: 10707114
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
  • Publication number: 20200098616
    Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.
    Type: Application
    Filed: March 25, 2019
    Publication date: March 26, 2020
    Inventors: Chih-Tang Peng, Shuen-Shin Liang, Keng-Chu Lin, Teng-Chun Tsai
  • Publication number: 20200083109
    Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Yen-Chun Huang, Chih-Tang Peng, Kuang-Yuan Hsu, Tai-Chun Huang, Tsu-Hsiu Perng, Tien-I Bao
  • Publication number: 20190371602
    Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Je-Ming Kuo, Yen-Chun Huang, Chih-Tang Peng, Tien-I Bao
  • Patent number: 10483169
    Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chun Huang, Chih-Tang Peng, Kuang-Yuan Hsu, Tai-Chun Huang, Tsu-Hsiu Perng, Tien-I Bao
  • Publication number: 20190341263
    Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 10468409
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure protruding from a semiconductor substrate. The fin structure includes a first portion and an overlying second portion. The first portion is formed of a material that is the same as that of the semiconductor substrate and different from that of the second portion. The semiconductor device structure also includes a liner structure and an isolation feature. The liner structure includes a carbon-doped silicon oxide film covering the semiconductor substrate and the first portion of the first fin structure and a nitrogen-containing film over the carbon-doped silicon oxide film. The isolation feature is over the nitrogen-containing film and surrounded by the liner structure.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ping Lee, Jian-Shiou Huang, Chih-Tang Peng, Sung-En Lin
  • Publication number: 20190318932
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 17, 2019
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Publication number: 20190287971
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure protruding from a semiconductor substrate. The fin structure includes a first portion and an overlying second portion. The first portion is formed of a material that is the same as that of the semiconductor substrate and different from that of the second portion. The semiconductor device structure also includes a liner structure and an isolation feature. The liner structure includes a carbon-doped silicon oxide film covering the semiconductor substrate and the first portion of the first fin structure and a nitrogen-containing film over the carbon-doped silicon oxide film. The isolation feature is over the nitrogen-containing film and surrounded by the liner structure.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Inventors: Szu-Ping LEE, Jian-Shiou HUANG, Chih-Tang PENG, Sung-En LIN
  • Patent number: 10418271
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Cheng-Tung Lin, Chih-Tang Peng, Chien-Hsun Wang, Bing-Hung Chen, Huan-Just Lin, Yung-Cheng Lu
  • Patent number: 10388531
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 10332746
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Patent number: 10325994
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Publication number: 20190164848
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a first insulation material layer in a portion of a trench between a first protruding structure and a second protruding structure over a substrate and performing a pre-treatment process on the first insulation material layer. The method further includes performing a first insulation material conversion process on the first insulation material layer and forming a second insulation material layer covering the first insulation material layer in the trench. In addition, a first distance between upper portions of the first protruding structure and the second protruding structure before performing the first insulation material conversion process is different from a second distance between the upper portions of the first protruding structure and the second protruding structure after performing the first insulation material conversion process.
    Type: Application
    Filed: July 27, 2018
    Publication date: May 30, 2019
    Inventors: Han-Pin CHUNG, Chih-Tang PENG, Tien-I BAO
  • Publication number: 20190131421
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Huang-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Patent number: 10269937
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Publication number: 20190006228
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
    Type: Application
    Filed: January 22, 2018
    Publication date: January 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
  • Publication number: 20180350655
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Teng-Chun TSAI, Bing-Hung CHEN, Chien-Hsun WANG, Cheng-Tung LIN, Chih-Tang PENG, De-Fang CHEN, Huan-Just LIN, Li-Ting WANG, Yung-Cheng LU
  • Publication number: 20180350693
    Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Yen-Chun Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang