Patents by Inventor Chih Teng HSU

Chih Teng HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942550
    Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
  • Patent number: 11921101
    Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Bonraybio Co., Ltd.
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei Chang, Chiung-Han Wang
  • Publication number: 20230028653
    Abstract: A method includes depositing a first semiconductor layer and a second semiconductor layer over a substrate; patterning the first semiconductor layer, the second semiconductor layer, and the substrate to form a first nanostructure, a second nanostructure, and a semiconductor fin; forming a recess in the first nanostructure and the second nanostructure, the recess exposing the semiconductor fin; epitaxially growing a first layer in the recess, a first portion of the first layer being disposed along a first sidewall of the first nanostructure, a second portion of the first layer being disposed along the semiconductor fin, the first portion of the first layer comprising two sidewalls extending toward a middle of the recess, the first portion of the first layer further comprising a first surface most distal from the first sidewall and directly interposed between the two sidewalls, the first portion being physically separated from the second portion; and epitaxially growing a second layer over the first portion of
    Type: Application
    Filed: January 3, 2022
    Publication date: January 26, 2023
    Inventors: Chih-Teng Hsu, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20220271171
    Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chang SU, Yan-Ting LIN, Chien-Wei LEE, Bang-Ting YAN, Chih Teng HSU, Chih-Chiang CHANG, Chien-I KUO, Chii-Horng LI, Yee-Chia YEO