Abstract: Some implementations described herein provide techniques and apparatuses for improving a uniformity of a flow of a gas across a semiconductor substrate in an etch tool. The etch tool includes an exhaust port located at a bottom center of a chamber of the etch tool. The etch tool further includes a flow-control subsystem that includes an impeller and a thermal component. As a result of the flow-control subsystem varying a rotational velocity of the impeller, and/or an amount of heat transferred from the thermal component, the uniformity of the flow of the gas across the semiconductor substrate may be improved. In this way, a uniformity of an etching rate may be increased and contamination defects due to a clustering of particulates may be decreased, resulting in an increase in a yield of semiconductor product fabricated using the etch tool.

Abstract: The present disclosure provides embodiments of a semiconductor device. In one embodiment, the semiconductor device includes a gate structure, a source/drain feature adjacent the gate structure, a first dielectric layer over the source/drain feature, an etch stop layer over the gate structure and the first dielectric layer, a second dielectric layer over the etch stop layer, a source/drain contact that includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer.

Abstract: A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

Abstract: Some embodiments provide a process of tunning sidewall profiles of gate openings prior to filling a replacement gate electrode layer therein to improve etching rate uniformity and stability during a subsequent gate electrode etch back process. Particularly, the profile sacrificial gate electrode is adjusted to be more straight profile rather than a bowl type profile, which reduces the seam void created in the replacement gate electrode during the replacement gate process. In some embodiments, tuning the profile of gate opening further includes performing a pullback etching process of the sidewall spacers prior to depositing gate dielectric layer and work function metal layer to achieve a wider opening for metal gate filling in the replacement gate process.

Abstract: Multiple-patterning techniques described herein enable forming fin structures of a semiconductor device in a manner that enables decreased fin-to-fin spacing of the fin structures while providing precise control over etching depth of the fin structures. In some implementations, an etch operation is performed to form a pattern in one or more mask layers that is used to etch a substrate to form the fin structures. The etch operation includes an advanced pulsing technique, in which a high-frequency radio frequency (RF) source and a low-frequency RF source are pulsed. Pulsing the high-frequency RF source and the low-frequency RF source in the etch operation reduces consumption of a thickness of the one or more mask layers which increases the aspect ratio of the pattern. This enables deeper etching of the substrate when forming the fin structures, which reduces the likelihood of under etching.

Abstract: A recovery layer (e.g., a layer of organic and/or tin-based material) is formed within recesses, in which adjacent MEOL or BEOL structures are formed, after plasma ashing and before a trimming process. The recovery layer preserves hardmask material and dielectric material such that upper surfaces of the adjacent MEOL or BEOL structures remain physically separated. As a result, the adjacent MEOL or BEOL remain electrically isolated and functional.

Abstract: A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

Abstract: A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: A method of making a semiconductor device includes steps related to forming source and drain wells of a transistor in a semiconductor substrate; forming a gate electrode of the transistor over the semiconductor substrate; forming an isolation structure in the semiconductor substrate adjacent to the transistor; and depositing a first inter-dielectric layer (ILD) material over the transistor and the isolation structure. The method also includes steps for depositing a capacitor film stack over the first ILD material, forming a pattern in the capacitor film stack over the isolation structure, and forming a capacitor plate by etching a conductive material of the capacitor film stack. Etching the conductive material includes performing a liquid etch process with a selectivity of at least 16 with regard to other materials in the capacitor film stack.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

Abstract: A plasma etching system generates a plasma above a wafer in a plasma etching chamber. The wafer is surrounded by a focus ring. The plasma etching system straightens a plasma sheath above the focus ring by generating a supplemental electric field above the focus ring.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a material layer over a semiconductor substrate; forming a plurality of spacer masks over the material layer; patterning the material layer into a plurality of masks below the spacer masks, wherein patterning the material layer comprises an atomic layer etching (ALE) process; and etching the semiconductor substrate through the masks.

Abstract: A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

Abstract: A method for manufacturing a semiconductor structure includes disposing a wafer in a processing chamber, in which the wafer is laterally surrounded by a focus ring. A plasma is formed in the processing chamber to process the wafer. A thickness of the focus ring is detected. A plasma direction of the plasma over a peripheral region of the wafer is adjusted according to the thickness of the focus ring.

Abstract: Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.