Patents by Inventor Chih-Ting Lin

Chih-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128127
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-l Fu, Chun-ya Chiu, Chi-Ting Wu, Chin-HUNG Chen, Yu-Hsiang Lin
  • Patent number: 11948820
    Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 2, 2024
    Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: Ming-Chien Chiu, Chih-Ming Lin, Cheng-Han Chou, Po-Ting Lee
  • Publication number: 20240107682
    Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.
    Type: Application
    Filed: April 21, 2023
    Publication date: March 28, 2024
    Inventors: Chao-Wei Chiu, Chih-Chiang Tsao, Jen-Jui Yu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240105481
    Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 28, 2024
    Inventors: MING-CHIEN CHIU, CHIH-MING LIN, CHENG-HAN CHOU, PO-TING LEE
  • Patent number: 11942750
    Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: March 26, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
  • Patent number: 11942550
    Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20240096958
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
  • Publication number: 20240096781
    Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240077914
    Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chih-Han Chang, Tsung-Ju Chiang, Chi-Hung Lin, Yen-Ting Liu
  • Publication number: 20240079972
    Abstract: The present invention relates to a shear deformation-type bimorphic piezoelectric actuator. The actuator includes at least a pair of shear deformation-type piezoelectric ceramic members which are polarized in the height direction thereof, coated with metal electrodes on both sides thereof and attached to opposite sides of a metal block to constitute a piezoelectric bimorph. The ceramic members are forced to undergo a face shear deformation or a resonance deformation upon receiving a driving voltage, whereby the metal block and the output head mounted thereon are driven to generate an elliptical motion, which in turn drives a rotor or a carriage to move. Taking advantage of the small dimension of the ceramic members and the enhanced displacement attributed to the piezoelectric bimorph structure, the piezoelectric actuator disclosed herein is suitable for manufacturing a miniature piezoelectric motor with high power output.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Inventors: Yung TING, Sheuan-Perng LIN, Suhail ABBAS, Chih-Hsuan YU
  • Publication number: 20240071952
    Abstract: A method includes depositing solder paste over first contact pads of a first package component. Spring connectors of a second package component are aligned to the solder paste. The solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. A device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. Each of the plurality of spring coils extends from the first package component to the second package component.
    Type: Application
    Filed: January 10, 2023
    Publication date: February 29, 2024
    Inventors: Chih-Chiang Tsao, Hsuan-Ting Kuo, Chao-Wei Chiu, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11915977
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
  • Publication number: 20240013836
    Abstract: Integration methods for prevention of floating gate 3D-NAND cell residual using a hybrid plug process in a super-deck structure and associated apparatus. A first desk layered structure comprising alternating isolation and conductor layers having a top isolation layer is formed over a substrate. A Silicon Nitride (SiN) layer is formed over the top isolation layer. An array of pillar holes vertically passing through the SiN layer and layers in the first deck layered structure are formed. The pillar holes are filled with a sacrificial film and an upper portion of the pillar holes are filled with a hybrid plug comprising first and second oxides. A second layered structure comprising alternating isolation and conductor layers having a bottom isolation layer is formed over the SiN layer, and an array of pillar holes are formed in the second deck layered structure. The hybrid plugs and sacrificial film is then removed using etching.
    Type: Application
    Filed: August 23, 2023
    Publication date: January 11, 2024
    Inventors: Chih Ting LIN, Jong Sun SEL
  • Publication number: 20230276621
    Abstract: An embodiment of a memory device may comprise a super-pillar formed through a plurality of sub-decks, a string of memory cells formed along the super-pillar, and respective regions of transition material disposed between respective sub-decks of the plurality of sub-decks, wherein the super-pillar comprises at least a first pillar formed through a first sub-deck of the plurality of sub-decks substantially aligned with a second pillar formed through a second sub-deck of the plurality of sub-decks. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 23, 2022
    Publication date: August 31, 2023
    Applicant: Intel NDTM US LLC
    Inventors: Chih Ting LIN, Nan WU, Xiangqin ZOU, Ngoc Quynh Hoa LE
  • Patent number: 10533963
    Abstract: A biosensor device includes a substrate, an oxide layer and a sensing wire. The oxide layer is disposed on the substrate. The sensing wire is disposed on the oxide layer. The sensing wire is provided to receive target biomolecules. The sensing wire includes at least one first section extending along a first direction and at least one second section extending along a second direction. The at least one first section is continuous with the at least one second section. The first direction is different from the second direction. The sensing wire has a width and a total length and a ratio of the total length to the width is larger than 500.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 14, 2020
    Assignee: MOBIOSENSE CORP.
    Inventors: Chih-Ting Lin, Yu-Hao Chen, Sheng-Yeh Chou
  • Patent number: 10466199
    Abstract: A biosensor device includes a substrate, a sensing transistor, an isolation layer and a main interface layer. The sensing transistor is formed on the substrate and including a bottom gate structure, a top gate structure and a semiconductor layer disposed between the bottom gate structure and the top gate structure. The bottom gate structure is electrically connected to the top gate structure. The isolation layer is formed on the sensing transistor for covering the sensing transistor, and includes a first opening. The main interface layer is disposed in the first opening for receiving biomolecules to be sensed. The main interface layer is electrically connected to the top gate structure.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 5, 2019
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Ting Lin, Shey-Shi Lu, Yu-Hao Chen, Sheng-Yeh Chou, I-Shun Wang, Che-Wei Huang, Pei-Wen Yen
  • Patent number: 10299678
    Abstract: An apparatus for detecting conductance parameter of high protein body fluid sample is provided. The apparatus includes at least one liquid collection element, and at least two electrodes horizontally aligned in the liquid collection element. Also provided are methods for detecting dehydration in a subject, comprising the steps of measuring the conductance parameter of the saliva of the subject.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: May 28, 2019
    Assignees: CHANG GUNG MEMORIAL HOSPITAL, CHIAYI, NATIONAL APPLIED RESEARCH LABORATORIES, NATIONAL TAIWAN UNIVERSITY
    Inventors: Jen-Tsung Yang, Leng-Chieh Lin, I-Neng Lee, Jo-Wen Huang, Jer-Liang Andrew Yeh, Ming-Yu Lin, Yen-Pei Lu, Chih-Ting Lin, Chia-Hong Gao
  • Publication number: 20180195991
    Abstract: A biosensor device includes a substrate, an oxide layer and a sensing wire. The oxide layer is disposed on the substrate. The sensing wire is disposed on the oxide layer. The sensing wire is provided to receive target biomolecules. The sensing wire includes at least one first section extending along a first direction and at least one second section extending along a second direction. The at least one first section is continuous with the at least one second section. The first direction is different from the second direction. The sensing wire has a width and a total length and a ratio of the total length to the width is larger than 500.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 12, 2018
    Inventors: Chih-Ting LIN, Yu-Hao CHEN, Sheng-Yeh CHOU