Patents by Inventor Chih-Ting SUN
Chih-Ting SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369309Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Tseng Chin LO, Molly CHANG, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
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Publication number: 20230359131Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.Type: ApplicationFiled: July 24, 2023Publication date: November 9, 2023Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
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Patent number: 11776948Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: GrantFiled: April 18, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
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Patent number: 11762302Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.Type: GrantFiled: May 24, 2021Date of Patent: September 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
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Publication number: 20220246600Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: ApplicationFiled: April 18, 2022Publication date: August 4, 2022Inventors: Tseng Chin LO, Molly CHANG, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
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Patent number: 11309307Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: GrantFiled: June 8, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
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Publication number: 20210278771Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
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Patent number: 11016398Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.Type: GrantFiled: June 14, 2018Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
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Publication number: 20200303366Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Tseng Chin LO, Molly CHANG, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
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Patent number: 10679980Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: GrantFiled: August 14, 2019Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
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Publication number: 20190384185Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.Type: ApplicationFiled: June 14, 2018Publication date: December 19, 2019Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
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Publication number: 20190371783Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: ApplicationFiled: August 14, 2019Publication date: December 5, 2019Inventors: Tseng Chin LO, Molly CHANG, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
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Patent number: 10388645Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: GrantFiled: July 27, 2018Date of Patent: August 20, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
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Patent number: 10283496Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: GrantFiled: April 11, 2017Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
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Publication number: 20180358348Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: ApplicationFiled: July 27, 2018Publication date: December 13, 2018Inventors: Tseng Chin LO, Molly CHANG, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
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Publication number: 20180006010Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.Type: ApplicationFiled: April 11, 2017Publication date: January 4, 2018Inventors: Tseng Chin LO, Molly Chang, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN