Abstract: A circulating current suppression method of a power system having a plurality of power modules is provided. Each power module includes a high-voltage bus, a low-voltage bus and a balance circuit having a neutral voltage. The circulating current suppression method includes: in each balance circuit, disposing a first capacitor electrically coupled between the high-voltage bus and the neutral voltage, and disposing a second capacitor electrically coupled between the neutral voltage and the low-voltage bus; acquiring a current effective value of an input of each power module; if detecting that the current effective value of at least one power module doesn't remain at a current reference value, determining that a circulating current occurs in the at least one power module; and operating the balance circuit of the at least one power module to charge the first capacitor or the second capacitor to regulate the neutral voltage for suppressing the circulating current.

Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.

Abstract: In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.

Abstract: A secondary node (SN) for requesting a master node (MN) to page a user equipment (UE) operating in dual connectivity (DC) with the MN and the SN receives, from a core network (CN), downlink traffic for the UE in an inactive state of a protocol for controlling radio resources, the inactive state being associated with a suspended radio connection between the UE and a radio access network (RAN) (802), and transmits, to the MN, a message that causes the MN to initiate RAN paging of the UE (804).

Abstract: A display device is provided. The display device includes a display module for displaying pictures and a viewing angle control module adjacent to the display module. The viewing angle control module includes a first substrate, a second substrate opposite to the first substrate, a viewing angle control medium disposed between the first substrate and the second substrate, and a touch layer disposed between the viewing angle control medium and the first substrate. The touch layer includes a bridge electrode and first touch electrodes disposed on the first substrate, and an insulation layer disposed between the bridge electrode and the first touch electrodes. The insulation layer has openings, and the first touch electrodes are electrically connected to the bridging electrode through the openings.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.

Abstract: A light emitter that operates through a display may cause display artifacts, even when the light emitter operates using non-visible wavelengths. To mitigate artifacts caused by a light emitter operating through a display, the display may have a higher density of thin-film transistor sub-pixels than emissive sub-pixels. This allows for a region in the display to include emissive sub-pixels but be free of thin-film transistor sub-pixels. The light emitter may operate through this region in the display. Additionally, to reduce the amount of space occupied in the inactive area of a display by gate driver circuitry, at least a portion of the gate driver circuitry may be positioned in the active area of the display. To accommodate the gate driver circuitry, emissive sub-pixels may be laterally shifted relative to corresponding thin-film transistor sub-pixels.

Abstract: A pixel structure includes a first light-emitting diode for emitting a first light, wherein the first light-emitting diode has a first semiconductor layer, a first light-emitting surface, and a first electrode under the first semiconductor layer away from the first light-emitting surface; a second light-emitting diode for emitting a second light, wherein the second light-emitting diode has a second semiconductor layer, a second light-emitting surface, and a second electrode under the second semiconductor layer away from the second light-emitting surface; a dielectric layer surrounding and contacting the first semiconductor layer and the second light-emitting diode and exposing the first light-emitting surface, the first electrode, the second light-emitting surface and the second electrode; a common conductive structure having a semiconductor layer and a metal layer; and a light-transmitting conductive layer covering and electrical connecting the first light-emitting diode, the second light-emitting diode and

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: An expansion cage assembly is configured to be installed onto two mounting plates, and is configured for an installation of an expansion card. The expansion cage assembly includes a supporting member, two side boards, a plurality of partitions and at least one expansion cage. The two side boards are connected to two opposite sides of the supporting member, respectively, and are detachably disposed the two mounting plates, respectively. The plurality of partitions are connected to the supporting member, and are disposed between the two side boards. The plurality of partitions are spaced apart from one another. The at least one expansion cage is disposed on one of the two side boards and the plurality of partitions.

Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.

Abstract: A wavelength conversion unit arrangement includes a carrier and a wavelength conversion unit. The wavelength conversion unit includes a wavelength conversion layer and a filter layer, and the filter layer attaches the wavelength conversion unit to the carrier. The filter layer has a first surface facing the carrier and a second surface opposite the first surface, and the first surface and the second surface have different textures.

Abstract: An electronic device, including a display module, a viewing angle switchable panel, a switching element, and a driving element, is provided. The display module has multiple first units and multiple second units. The first units have a first color, and the second units have a second color. The first color and the second color are different. The switching element is used to switch the viewing angle switchable panel between a first viewing angle mode and a second viewing angle mode. The driving element is used to provide a first data voltage to at least one of the first units of the display module in the first viewing angle mode, and provide a second data voltage to the at least one of the first units in the second viewing angle mode. The first data voltage and the second data voltage are different.

Abstract: A semiconductor device includes in a transistor layer, components of corresponding transistors (transistor components); in corresponding layers below the transistor layer (sub-TR layers), various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and which are included because the semiconductor device has a buried power rail (BPR) architecture; and in corresponding layers over the transistor layer (supra-TR layers), various dummy structures (dummy supra-TR structures) which are included as artifacts resulting from the semiconductor device being based on a dual-architecture-compatible design which is substantially equally suitable either to adaptation into a non-BPR architecture or adaptation into the BPR architecture; and the semiconductor device being an inductor.

Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.

Abstract: An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: An information handling system may include a first member, a second member, and one or more hinge assemblies for coupling the first and second members, where the one or more hinge assemblies comprise a central assembly, a first and a second orbit mechanism configured to couple to the first and second members respectively, a first primary shaft coupling a first pair of link bars to the central assembly and to each other, a first secondary shaft coupling the first pair of link bars to each other and to the first orbit mechanism via a first track comprising an elongated opening, a second primary shaft coupling a second pair of link bars to the central assembly and to each other, and a second secondary shaft coupling the second pair of link bars to each other and to the second orbit mechanism via a second track comprising an elongated opening.

Abstract: The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.