Patents by Inventor Chih-To Hsieh

Chih-To Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143880
    Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.
    Type: Application
    Filed: January 27, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Wen LIN, Bogdan TUTUIANU, Florentin DARTU, Wei-Chih HSIEH, Osamu TAKAHASHI
  • Publication number: 20240139301
    Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 2, 2024
    Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
  • Patent number: 11971498
    Abstract: Hybrid positioning methods and electronic apparatuses are provided. A representative method includes: obtaining initial location information; computing initial moving information based upon the sensor readings; computing estimated location information based on the initial moving information and the initial location information; acquiring geographical location readings if a location update condition is satisfied; generating reference location information based on the geographical location readings acquired; comparing the estimated location information with the reference location information to obtain a deviation information; computing a calibrated moving information based on the estimated location information and the deviation information; and computing a calibrated location information based on the deviation information, calibrated moving information and the estimated location information.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 30, 2024
    Assignee: CM HK LIMITED
    Inventors: Yu-Kuen Tsai, Ching-Lin Hsieh, Chien-Chih Hsu
  • Patent number: 11974228
    Abstract: An apparatus (e.g., an access point (AP) or a non-AP station (STA)) detects a non-primary subband of an operating bandwidth comprising a primary subband and the non-primary subband to be idle. The apparatus controls a transmit power in performing transmission on at least the non-primary subband.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 30, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Kai Ying Lu, Hung-Tao Hsieh, Yen-Shuo Lu, Chao-Chun Wang, James Chih-Shi Yee, Yongho Seok
  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Publication number: 20240128955
    Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.
    Type: Application
    Filed: April 24, 2023
    Publication date: April 18, 2024
    Inventors: Shao-Yu Steve Wang, Chien-Te Wu, Shang-Chih Hsieh, Nick Tsai
  • Patent number: 11963097
    Abstract: Communications between an access point (AP) and a non-AP station (STA) are established in a plurality of frequency segments within a basic service set (BSS) bandwidth or on at least a first link and a second link. An extreme-high-throughput (EHT) subchannel selective transmission (SST) operation is performed between the AP and the non-AP STA in the plurality of frequency segments or on the first link and the second link. A trigger-enabled target wake time (TWT) session period (SP) for the EHT SST operation by either indicating one of the plurality of frequency segments as containing a resource unit (RU) allocation addressed to the non-AP STA or indicating one of the first link and the second link on which an operating frequency segment is located during the TWT SP.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: April 16, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Yongho Seok, Hung-Tao Hsieh, Jianhan Liu, James Chih-Shi Yee
  • Publication number: 20240119200
    Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Jen Chen, Chien-Chih Wang, Wen-Wen Hsieh, Ying-Yi Teng
  • Publication number: 20240120203
    Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
  • Patent number: 11952246
    Abstract: Disclosed is a brake winch with reverse release and self-locking functions. The brake winch has a housing with first and second side walls, an accommodating space, and an auxiliary bracket part. A rotating disk is screwed in the accommodating space. A main shaft is screwed on one side of the rotating disk in an interlocking manner. A screw adapter is screwed on the second side wall, and includes an inner connection end that is assembled with the main shaft, and its external end has a threaded groove. The axial displacement of a driving screw, which is screwed on the auxiliary bracket, is matched with the difference of forward and reverse rotation to form a screwing transmission or release mode between the stud section and the thread groove. A friction driving mechanism must prompt the drive screw, the clamping plate and the screw adapter to be in a tightly synchronized state.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: April 9, 2024
    Inventor: Wu-Chih Hsieh
  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Publication number: 20240102860
    Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Cheng Chih HSIEH, Tien Chi WU, Ming-Long LEE, Yu-Hsuan LIN, Tsung-I LIN, Chien-Hao MA
  • Patent number: 11943643
    Abstract: An access point (AP) and a station (STA) communicate with each other, with the AP indicating to the STA either or both of a preamble detection (PD) channel and a signaling (SIG) content channel and with the STA being initially monitoring a primary frequency segment of a plurality of frequency segments in an operating bandwidth of the AP. A downlink (DL) or triggered uplink (UL) communication is performed between the AP and the STA during a transmission opportunity (TXOP) such that: (i) during the TXOP, the STA monitors a preamble on the PD channel and decodes a SIG content on the SIG content channel; and (ii) after an end of the TXOP, the STA switches to the primary frequency segment.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: March 26, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Kai Ying Lu, Yongho Seok, Hung-Tao Hsieh, Cheng-Yi Chang, James Chih-Shi Yee, Jianhan Liu, Po-Yuen Cheng
  • Patent number: 11942945
    Abstract: A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Huaixin Xian, Qingchao Meng, Yang Zhou, Shang-Chih Hsieh
  • Patent number: 11936238
    Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: March 19, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hsin-Chih Chen, Hung-Chieh Lin, Chao-Lung Kuo, Yi-Ping Hsieh, Chien-Shien Lee
  • Publication number: 20240085804
    Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chih HSIEH, Ming-Hsiao WENG
  • Publication number: 20240087879
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20240077922
    Abstract: An electronic system using a USB type-C port and an abnormal elimination method thereof are provided. After sending a hard reset request to a power adapter, a host device determines whether to enter an error recovery state according to whether an initialization signal is at a first preset level for a first preset time, so that the initialization signal is changed to a second preset level, or whether to force the initialization signal to change to the second preset level according to whether the initialization signal is at the first preset level for a second preset time.
    Type: Application
    Filed: November 30, 2022
    Publication date: March 7, 2024
    Applicant: Acer Incorporated
    Inventors: Yuan-Yi Li, Ming-Feng Hsieh, Chun-Chih Kuo
  • Publication number: 20240073980
    Abstract: A first base station providing to the UE configuration data related to a second base station and at least one condition for connecting to the second base station in order to operate in dual connectivity with the first base station and the second base station (1802). The base station receiving from the UE a first indication that the UE has conditionally applied the configuration data (1804). Subsequently to receiving the first indication, the base station receives a second indication that the at least one condition is satisfied (1806).
    Type: Application
    Filed: October 2, 2020
    Publication date: February 29, 2024
    Inventors: Chih-Hsiang Wu, Jing Hsieh
  • Publication number: 20240069449
    Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chih HSIEH, Yen-Liang CHEN