Patents by Inventor Chih-Tsun Huang

Chih-Tsun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210201127
    Abstract: An adaptive learning power modeling method includes: sampling at least one of a plurality of network components to form a power consumption evaluation network according to at least one parameter within a parameter range; evaluating a predictive power consumption of a to-be-measured circuit by the power consumption evaluation network; training and evaluating an actual power consumption and the predictive power consumption of the to-be-measured circuit by the power consumption evaluation network to obtain an evaluation result; and performing training according to the evaluation result to determine whether to change the power consumption evaluation network.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua CHEN, Jing-Jia LIOU, Chih-Tsun HUANG, Juin-Ming LU
  • Publication number: 20200193275
    Abstract: A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.
    Type: Application
    Filed: January 15, 2019
    Publication date: June 18, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua CHEN, Chun-Chen CHEN, Chih-Tsun HUANG, Jing-Jia LIOU, Chun-Hung LAI, Juin-Ming LU
  • Patent number: 10365829
    Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 30, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua Chen, Che-Wei Hsu, Juin-Ming Lu, Wei-Shiang Lin, Jing-Jia Liou, Chih-Tsun Huang
  • Publication number: 20180074702
    Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.
    Type: Application
    Filed: December 27, 2016
    Publication date: March 15, 2018
    Inventors: Yao-Hua Chen, Che-Wei Hsu, Juin-Ming Lu, Wei-Shiang Lin, Jing-Jia Liou, Chih-Tsun Huang
  • Publication number: 20170169150
    Abstract: A method for system simulation includes the steps of: simulating the operation of a first circuit during N clock periods based on a first model and a simulation granularity, and adjusting the simulation granularity based on the input signal or the output signal corresponding to the first model. A non-transitory computer-readable recording medium corresponding to the method is also provided.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 15, 2017
    Inventors: YAO-HUA CHEN, CHE-WEI HSU, JUIN-MING LU, TING-SHUO HSU, JING-JIA LIOU, CHIH-TSUN HUANG
  • Patent number: 7904768
    Abstract: A probing system for an integrated circuit device, which transmits a testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes a test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform a test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.
    Type: Grant
    Filed: May 3, 2008
    Date of Patent: March 8, 2011
    Assignee: National Tsing Hua University
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Yu-Tsao Hsing
  • Patent number: 7861070
    Abstract: The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the registers in a first cycle and register content of each of the registers in a second cycle, in which the second cycle is next to the first cycle; (2) calculating difference of the register content of each of the registers in the second cycle and the register content of each of the registers in the first cycle; and (3) packing the differences of the register contents into data trace packets, in which the differences of the register contents of adjacent registers are condensed into a single data trace packet when the differences of the register contents of the adjacent registers are zeroes.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: December 28, 2010
    Assignee: National Tsing Hua University
    Inventors: Chih Tsun Huang, Yen Ju Ho, Ming Chang Hsieh
  • Publication number: 20100172492
    Abstract: A scheduling method for ECC computation processed in a plurality of arithmetic units comprises a coarse-grained scheduling step for systematically scheduling an ECC computation operation and a fine-grained scheduling step for refining the scheduled ECC computation operation.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 8, 2010
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: JYU YUAN LAI, CHIH TSUN HUANG
  • Patent number: 7675309
    Abstract: A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system comprising a test head having a first transceiving module; a test station having a test unit couple to the test head to perform test operation; a communication module having a second transceiving module configured to exchange data with the first transceiving module; an integrated circuit device having at least one core circuit being tested; and at least one test module having a self-test circuit couple to the core circuit and the communication module for performing the core circuit self-testing.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: March 9, 2010
    Assignee: National Tsing Hua University
    Inventors: Cheng Wen Wu, Chih Tsun Huang, Yu Tsao Hsing
  • Publication number: 20090313460
    Abstract: The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the registers in a first cycle and register content of each of the registers in a second cycle, in which the second cycle is next to the first cycle; (2) calculating difference of the register content of each of the registers in the second cycle and the register content of each of the registers in the first cycle; and (3) packing the differences of the register contents into data trace packets, in which the differences of the register contents of adjacent registers are condensed into a single data trace packet when the differences of the register contents of the adjacent registers are zeroes.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 17, 2009
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHIH TSUN HUANG, YEN JU HO, MING CHANG HSIEH
  • Publication number: 20090201039
    Abstract: A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system comprising a test head having a first transceiving module; a test station having a test unit couple to the test head to perform test operation; a communication module having a second transceiving module configured to exchange data with the first transceiving module; an integrated circuit device having at least one core circuit being tested; and at least one test module having a self-test circuit couple to the core circuit and the communication module for performing the core circuit self-testing.
    Type: Application
    Filed: April 16, 2009
    Publication date: August 13, 2009
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHENG WEN WU, CHIH TSUN HUANG, YU TSAO HSING
  • Publication number: 20080209293
    Abstract: A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.
    Type: Application
    Filed: May 3, 2008
    Publication date: August 28, 2008
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Cheng Wen WU, Chih Tsun Huang, Yu Tsao Hsing
  • Publication number: 20070232240
    Abstract: The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.
    Type: Application
    Filed: June 12, 2007
    Publication date: October 4, 2007
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Yu-Tsao Hsing
  • Publication number: 20060252375
    Abstract: The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.
    Type: Application
    Filed: August 12, 2005
    Publication date: November 9, 2006
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Yu-Tsao Hsing
  • Patent number: 7117409
    Abstract: In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: October 3, 2006
    Assignee: National Tsing Hua University
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Chih-Wea Wang, Kao-Liang Cheng
  • Patent number: 7065689
    Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in ?45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: June 20, 2006
    Assignees: Spirox Corporation/National, Tsing Hua University
    Inventors: Sau-Kwo Chiu, Jen-Chieh Yeh, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
  • Patent number: 6934900
    Abstract: A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: August 23, 2005
    Assignee: Global Unichip Corporation
    Inventors: Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
  • Publication number: 20040233767
    Abstract: A method and system of fault patterns oriented defect diagnosis for memories can analyze and recognize fault patterns and failure patterns after Memory Error Catches and Analyses (MECA) are done. The existent fault patterns are compared with a pre-simulated and grouped defect dictionary that defines possible defects of different fault patterns, and the defects of memories caused from their manufacturing process or circuit layout can be detected.
    Type: Application
    Filed: April 7, 2004
    Publication date: November 25, 2004
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee
  • Publication number: 20040221109
    Abstract: In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.
    Type: Application
    Filed: December 12, 2003
    Publication date: November 4, 2004
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Chih-Wea Wang, Kao-Liang Cheng
  • Publication number: 20040015756
    Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in −45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.
    Type: Application
    Filed: June 24, 2003
    Publication date: January 22, 2004
    Inventors: Sau-Kwo Chiu, Jen-Chieh Yeh, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu