Abstract: A solar cell module includes a first substrate, a second substrate, at least one cell unit, a first packaging film, a second packaging film, a first protective layer, a second protective layer, and a plurality of support members. The first substrate and the second substrate are disposed opposite to each other. The cell unit is disposed between the first substrate and the second substrate. The first packaging film is disposed between the cell unit and the first substrate. The second packaging film is disposed between the cell unit and the second substrate. The first protective layer is disposed between the cell unit and the first packaging film. The second protective layer is disposed between the cell unit and the second packaging film. The support members are respectively disposed between the first packaging film and the second packaging film and surround at least two opposite sides of the cell unit.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A method for preparing a semiconductor device structure with features at different levels. The method includes forming a target layer over a semiconductor substrate; forming a plurality of first energy-sensitive patterns over the target layer; performing an energy treating process to transform at least a portion of each of the first energy-sensitive patterns into a first treated portion; forming a lining layer conformally covering the first energy-sensitive patterns, wherein a first opening is formed over the lining layer and between the first energy-sensitive patterns; filling the first opening with a second energy-sensitive pattern; and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.

Abstract: A semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

Abstract: The present disclosure relates to a semiconductor device with an air gap below a landing pad and a method for forming the semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first energy-sensitive patterns over the target layer. The method also includes forming a lining layer conformally covering the first energy-sensitive patterns. A first opening is formed over the lining layer and between the first energy-sensitive patterns. The method further includes filling the first opening with a second energy-sensitive pattern, and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.

Abstract: A semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

Abstract: The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die, a memory die, and a sensor die. The logic die includes a front surface. The memory die includes a front surface positioned on the front surface of the logic die, and a back surface opposite to the front surface of the memory die. The sensor die includes a front surface positioned on the back surface of the memory die, a back surface opposite to the front surface of the sensor die, a sensor unit located at the back surface of the sensor die, a color filter positioned on the back surface of the sensor die, and a micro-lens positioned on the color filter.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first energy-sensitive patterns over the target layer. The method also includes forming a lining layer conformally covering the first energy-sensitive patterns. A first opening is formed over the lining layer and between the first energy-sensitive patterns. The method further includes filling the first opening with a second energy-sensitive pattern, and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.

Abstract: A method for preparing a semiconductor device structure with features at different levels. The method includes forming a target layer over a semiconductor substrate; forming a plurality of first energy-sensitive patterns over the target layer; performing an energy treating process to transform at least a portion of each of the first energy-sensitive patterns into a first treated portion; forming a lining layer conformally covering the first energy-sensitive patterns, wherein a first opening is formed over the lining layer and between the first energy-sensitive patterns; filling the first opening with a second energy-sensitive pattern; and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.

Abstract: The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die, a memory die, and a sensor die. The logic die includes a front surface. The memory die includes a front surface positioned on the front surface of the logic die, and a back surface opposite to the front surface of the memory die. The sensor die includes a front surface positioned on the back surface of the memory die, a back surface opposite to the front surface of the sensor die, a sensor unit located at the back surface of the sensor die, a color filter positioned on the back surface of the sensor die, and a micro-lens positioned on the color filter.

Abstract: The present application discloses a semiconductor device having a landing pad with spacers. The semiconductor device includes a first insulating layer, a second insulating layer, a conductive pillar and spacers. The first insulating layer is disposed on a substrate. The second insulating layer is disposed on the first insulating layer. The conductive pillars are disposed in the first insulating layer and penetrates through the second insulating layer. The spacers are disposed on sidewalls of the conductive pillars.

Abstract: An information handling system with a wireless charging device may include a processor; a memory; a power management unit (PMU); an antenna controller to provide instructions to a radio to cause an antenna to transceive wirelessly with a network; a wireless charging scheduling controller configured to: receive transmission scheduling data from the antenna controller descriptive of when the radio is transmitting and receiving data to and from the network; and initiate, at a charging coil of the wireless charging device, a charging procedure to wirelessly charge a power storage device when the transmission scheduling data indicates that the radio is receiving data from the network or is idle.

Abstract: The present disclosure relates to a semiconductor device with an air gap below a landing pad and a method for forming the semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

Abstract: The present disclosure provides a semiconductor device with an air gap between gate-all-around (GAA) transistors and a method for forming the semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed over a semiconductor substrate. At least one of the first gate stack and the second gate stack includes a plurality of gate layers, and the first gate stack and the second gate stack have an air gap therebetween. The semiconductor device also includes a first gate structure and a second gate structure disposed over the first gate stack and the second gate stack, respectively, and a first dielectric layer surrounds lower sidewalls of the first gate structure and lower sidewalls of the second gate structure. A width of the first gate structure is greater than a width of the first plug.

Abstract: The present disclosure provides a semiconductor device with an air gap between gate-all-around (GAA) transistors and a method for forming the semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed over a semiconductor substrate. At least one of the first gate stack and the second gate stack includes a plurality of gate layers, and the first gate stack and the second gate stack have an air gap therebetween. The semiconductor device also includes a first gate structure and a second gate structure disposed over the first gate stack and the second gate stack, respectively, and a first dielectric layer surrounds lower sidewalls of the first gate structure and lower sidewalls of the second gate structure. A width of the first gate structure is greater than a width of the first plug.

Abstract: The present application discloses a semiconductor device having a landing pad with spacers and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer, a second insulating layer, a conductive pillar and spacers. The first insulating layer is disposed on a substrate. The second insulating layer is disposed on the first insulating layer. The conductive pillars are disposed in the first insulating layer and penetrates through the second insulating layer. The spacers are disposed on sidewalls of the conductive pillars.

Abstract: The present application discloses a semiconductor device having a landing pad with spacers. The semiconductor device includes a first insulating layer, a second insulating layer, a conductive pillar and spacers. The first insulating layer is disposed on a substrate. The second insulating layer is disposed on the first insulating layer. The conductive pillars are disposed in the first insulating layer and penetrates through the second insulating layer. The spacers are disposed on sidewalls of the conductive pillars.

Abstract: The present application discloses a semiconductor device having a landing pad with spacers and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer, a second insulating layer, a conductive pillar and spacers. The first insulating layer is disposed on a substrate. The second insulating layer is disposed on the first insulating layer. The conductive pillars are disposed in the first insulating layer and penetrates through the second insulating layer. The spacers are disposed on sidewalls of the conductive pillars.

Abstract: The present disclosure provides a semiconductor device with a porous dielectric structure for reducing capacitive coupling between conductive features. The semiconductor device includes a substrate; a gate structure positioned above the substrate; two source/drain regions positioned adjacent to two sides of the gate structure; two porous spacers positioned between the source/drain regions and the gate structure, wherein a porosity of the two porous spacers is between about 25% and about 100%; a porous capping layer positioned on the gate structure and between the two porous spacers, wherein a porosity of the porous capping layer is between about 25% and about 100%; and an insulating layer disposed over the two porous spacers and the porous capping layer.