Patents by Inventor Chih-Tsung Yao
Chih-Tsung Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9685395Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.Type: GrantFiled: March 5, 2015Date of Patent: June 20, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
-
Patent number: 9557764Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.Type: GrantFiled: December 28, 2015Date of Patent: January 31, 2017Assignee: MEDIATEK INC.Inventors: Chen-Feng Chiang, Kai-Hsin Chen, Ming-Shi Liou, Chih-Tsung Yao
-
Publication number: 20160132071Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Inventors: Chen-Feng CHIANG, Kai-Hsin CHEN, Ming-Shi LIOU, Chih-Tsung YAO
-
Patent number: 9256245Abstract: A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.Type: GrantFiled: January 22, 2015Date of Patent: February 9, 2016Assignee: MEDIATEK INC.Inventors: Chen-Feng Chiang, Kai-Hsin Chen, Ming-Shi Liou, Chih-Tsung Yao
-
Publication number: 20150286243Abstract: A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.Type: ApplicationFiled: January 22, 2015Publication date: October 8, 2015Inventors: Chen-Feng CHIANG, Kai-Hsin CHEN, Ming-Shi LIOU, Chih-Tsung YAO
-
Publication number: 20150179550Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.Type: ApplicationFiled: March 5, 2015Publication date: June 25, 2015Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
-
Patent number: 8981562Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.Type: GrantFiled: June 6, 2008Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
-
Patent number: 8826207Abstract: A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.Type: GrantFiled: December 28, 2007Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cliff Hou, Gwan Sin Chang, Cheng-Hung Yeh, Chih-Tsung Yao
-
Patent number: 8286114Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.Type: GrantFiled: August 2, 2007Date of Patent: October 9, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Mong Song Liang, Sheng-Chen Chung, Chih-Tsung Yao, Jung-Hui Kao, Chung Long Cheng, Gary Shen, Gwan Sin Chang
-
Publication number: 20090077507Abstract: A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.Type: ApplicationFiled: December 28, 2007Publication date: March 19, 2009Inventors: Cliff Hou, Gwan Sin Chang, Cheng-Hung Yeh, Chih-Tsung Yao
-
Publication number: 20080263492Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.Type: ApplicationFiled: August 2, 2007Publication date: October 23, 2008Inventors: Harry Chuang, Kong-Beng Thei, Mong Song Liang, Sheng-Chen Chung, Chih-Tsung Yao, Jung-Hui Kao, Chung Long Cheng, Gary Shen, Gwan Sin Chang
-
Publication number: 20080237885Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.Type: ApplicationFiled: June 6, 2008Publication date: October 2, 2008Inventors: Harry Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
-
Patent number: 7404167Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.Type: GrantFiled: December 27, 2005Date of Patent: July 22, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
-
Publication number: 20060188824Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.Type: ApplicationFiled: December 27, 2005Publication date: August 24, 2006Inventors: Harry Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen