Patents by Inventor Chih Tung Hsu

Chih Tung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240377755
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 12044977
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Publication number: 20230367229
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 11726408
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Publication number: 20220357652
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 11402747
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Publication number: 20210255540
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 10996558
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 10620530
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Publication number: 20200050102
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Publication number: 20190033706
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 31, 2019
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 8056058
    Abstract: The method for generating test cases for a software program includes the step of setting a plurality of reference points in accordance with a sentence of the software program. The tracing pairs each including an initial test case as well as its adjacent vertex are set if one of them is among the reference points and the other one is not among the reference points. The essential test cases are chosen from the tracing pairs.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 8, 2011
    Assignee: National Tsing Hua University
    Inventors: Chin Yu Huang, Jun Ru Chang, Chih Tung Hsu
  • Publication number: 20080288925
    Abstract: The method for generating test cases for a software program includes the step of setting a plurality of reference points in accordance with a sentence of the software program. The tracing pairs each including an initial test case as well as its adjacent vertex are set if one of them is among the reference points and the other one is not among the reference points. The essential test cases are chosen from the tracing pairs.
    Type: Application
    Filed: September 27, 2007
    Publication date: November 20, 2008
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chin Yu Huang, Jun Ru Chang, Chih Tung Hsu
  • Publication number: 20050289488
    Abstract: A mask defect detection system. The mask defect detection system comprises a first processing device, a second processing device, a third processing device, and a storage device. The first processing device processes mask design information to generate first writer-formatted mask information, wherein the first processing device comprises a first processing module. The second processing device processes mask design information to generate second writer-formatted mask information. The third processing device compares the first and second writer-formatted mask information to find differences therebetween. The storage device stores the mask design information, and the first and second writer-formatted mask information.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: I-Ju Chou, Chih-Tung Hsu