Abstract: A detection circuit and a detection method are provided. The detection circuit is suitable for a system-on-chip (SoC). The SoC is coupled to an alarm pin of a DDR4 memory through a connection pad, and the detection circuit includes a control circuit coupled to the connection pad. In response to the DDR4 memory performing a refresh process or a specific event occurring, the control circuit outputs a test signal with a first voltage level to the connection pad, and determines whether a voltage level of the connection pad is tied to a second voltage level. In response to determining that the voltage level of the connection pad is tied to the second voltage level, the control circuit outputs an interrupt signal to a CPU of the SoC, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not controlled normally by the DDR4 memory.

Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.

Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.

Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.

Abstract: A method includes obtaining a feature vector for each cell in a group of cells. The feature vector for a cell includes a score value for each feature in a set of features selected for characterizing the group of cells. The method includes clustering cells in the group into a selected number of clusters, based on distances between end points of feature vectors of the cells. The method includes generating a list of ranked critical cells in the selected number of clusters based on a list of prioritized features associated with the set of features. The method includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Abstract: A memory device, a semiconductor device and their manufacturing methods are provided. One of the methods may include: providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad; stacking the plurality of second dies on the first die, the second pads and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped; forming a connecting hole passing through the second dies; and forming a conductive body filling the connecting hole and connecting the first pad and the second pads. This method simplifies the manufacturing process of a semiconductor device, reduces the cost thereof, and improves the production yield.

Abstract: Provided are a chip and a memory, relating to the technical field of semiconductors, and intended to solve the technical problem of low qualification rate of chips. The chip includes a base in which a through hole penetrating through the base is provided. A conductive column is provided in the through hole. A first surface of the base is provided with a first annular groove which surrounds the conductive column. A first isolator is provided in the first annular groove, and a first air gap extending along a circumferential direction of the first annular groove is formed in the first isolator.

Abstract: A method of foreground auto-calibrating data reception window for a DRAM system is disclosed. The method comprises receiving data strobe and data from a DRAM of the DARM system, capturing a data strobe clock according to the received data strobe, generating three time points with a period of the data strobe clock, sampling the data at the three time points, to obtain three sampled data, determining whether to adjust positions of the three time points according to a comparison among the three sampled data, and configuring the valid data reception window according to the positions of the three time points when determining not to adjust the positions of the three time points.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A microscope-based system and a method for image-guided microscopic illumination are provided. The microscope-based system for image-guided microscopic illumination comprises a microscope, an illuminating assembly, an imaging assembly, a first processing module, and a second processing module. The microscope comprises a stage, and the stage is configured to be loaded with a sample. The imaging assembly comprises a camera. The processing modules are coupled to the microscope, the imaging assembly, and the illuminating assembly.

Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

Abstract: A lens structure includes a lens cone, at least one lens and an acrylate adhesive. The lens cone includes at least one contacting structure. The lens is disposed within the lens cone and abuts against the contacting structure. The acrylate adhesive covers an interface between the lens cone and the lens, wherein a coverage area of the acrylate adhesive accounts for more than 70% of a surface area of a side surface of the lens.

Abstract: A wireless implant and associated system for motor function recovery after spinal cord injury, and more particularly a multi-channel wireless implant with small package size. The wireless implant can further be used in various medical applications, such as retinal prostheses, gastrointestinal implant, vagus nerve stimulation, and cortical neuromodulation. The system also includes a method and its implementation to acquire the impedance model of the electrode-tissue interface of the implant.

Abstract: A semiconductor structure and a forming method thereof are provided. The forming method of the semiconductor structure includes that: a wafer having a front surface and a back surface is provided, a conductive plug being provided in the wafer, the conductive plug extending from the front surface to the back surface and the conductive plug having a bottom surface located in the wafer; an etching process is performed on the back surface of the wafer to form a groove exposing at least the bottom surface of the conductive plug; and a functional layer covering the bottom surface of the conductive plug is formed.

Abstract: An apparatus for electroporating cells with a cargo includes electrodes defining a path for a fluid including the cells and the cargo to flow, a power source coupled across the electrodes, and a control circuit. In some examples, the control circuit is configured to detect a decrease in an induced current due to an increase in a resistance between the electrodes, and control the power source to increase the induced current to maintain an electric field between the electrodes. A future value of the resistance between the electrodes may be predicted based on previous values of the resistance. In other examples, the control circuit is configured to detect parameters of the fluid flowing between the electrodes, and control the power source to generate or stop generating electrical pulses in response to detecting the parameters. Other example apparatuses, and methods of electroporating cells with a cargo is also disclosed.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A wireless implant and associated system for motor function recovery after spinal cord injury, and more particularly a multi-channel wireless implant with small package size. The wireless implant can further be used in various medical applications, such as retinal prostheses, gastrointestinal implant, vagus nerve stimulation, and cortical neuromodulation. The system also includes a method and its implementation to acquire the impedance model of the electrode-tissue interface of the implant.

Abstract: Apparatus and methods may be provided that may include a single bracket (e.g., a single universal support or anchor bracket) capable of operably mounting or supporting multiple diverse configurations of system hardware components (e.g., such as solid state drive (SSD) cards) to an existing motherboard or other system support component/surface on or within the same system chassis of an information handling system.

Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.