Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A method includes providing semiconductor channel layers over a substrate; forming a first dipole layer wrapping around the semiconductor channel layers; forming an interfacial dielectric layer wrapping around the first dipole layer; forming a high-k dielectric layer wrapping around the interfacial dielectric layer; forming a second dipole layer wrapping around the high-k dielectric layer; performing a thermal process to drive at least some dipole elements from the second dipole layer into the high-k dielectric layer; removing the second dipole layer; and forming a work function metal layer wrapping around the high-k dielectric layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first gate electrode layer, a second gate electrode layer disposed over and aligned with the first gate electrode layer, and a gate isolation structure disposed between the first gate electrode layer and the second gate electrode layer. The gate isolation structure includes a first surface and a second surface opposite the first surface. At least a portion of the first surface is in contact with the first gate electrode layer. The second surface includes a first material and a second material different from the first material, and at least a portion of the second surface is in contact with the second gate electrode layer.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: A reflective element driving module includes a first reflective element, a second reflective element, and a driving assembly. The first reflective element has a first reflective surface, disposed to correspond to the incident light, wherein the light has an optical axis. The second reflective element has a second reflective surface, disposed to correspond to the light reflected by the first reflective element, and is movable relative to the first reflective element. The driving assembly is configured to drive the second reflective element to move relative to the first reflective element, wherein the first reflective surface and the second reflective surface face different directions.

Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: An optical system is provided and includes a fixed assembly, a movable element, a movable assembly, a driving module and a stopping assembly. The fixed assembly defines a main axis. The movable element is movable relative to the fixed assembly and is connected to a first optical element. The movable assembly is connected to the movable element. The driving module is configured to drive the movable assembly so as to drive the movable element to move relative to the fixed assembly. The stopping assembly is configured to limit the range of motion of the movable element.

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a metal gate layer for the P-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a first layer, and a fill layer over the first layer. The gate structure includes a protection layer formed over the fill layer of the gate structure, and the protection layer is separated from the first layer by the fill layer.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial gate dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the gate all around core transistor.

Abstract: A video decoder receives to-be-decoded data from a bitstream for a block of pixels to be decoded as a current block of a current picture of the video. The video decoder generates a first prediction of the current block based on a first prediction mode that is selected from a first candidate list. The video decoder generates a second prediction of the current block based on a second prediction mode that is selected from a second candidate list. The video decoder generates a combined prediction for the current block based on the first prediction and the second prediction. The video decoder reconstructs the current block by using the combined prediction.

Abstract: A video coder receives data from a bitstream for a block of pixels to be encoded or decoded as a current block of a current picture of a video. Upon determining that an applied block setting of the current block satisfies a threshold condition, the video coder generates a first prediction based on a first motion information for a first prediction unit of the current block. The video coder generates a second prediction based on a second motion information for a second prediction unit of the current block. The video coder generates a third prediction based on the first and second motion information for an overlap prediction region that is defined based on a partitioning between the first prediction unit and the second prediction unit. The video coder encodes or decodes the current block by using the first, second, and third predictions.

Abstract: A method and apparatus of prediction for video coding using MH (Multiple Hypothesis) mode are disclosed. According to this method, a block is partitioned into a first partition and a second partition. A first candidate and a second candidate are derived for the first and second partitions respectively. At least one of the first candidate and the second candidate is derived using a candidate list derived for a regular Merge mode (or also called as normal Merge mode). An MH prediction generated by blending a first prediction corresponding to a first candidate and a second prediction corresponding to a second candidate, and the MH prediction is applied to a part of the current block.

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: In a method and apparatus for video coding using Low-Frequency Non-Separable Transform (LFNST) mode, a coding unit (CU) is partitioned into one or more transform blocks (TBs). A syntax is determined at an encoder side or at a decoder side, where the determining step is performed by signaling the syntax at the encoder side or by parsing the syntax at the decoder side if one or more conditions are satisfied. The syntax indicates whether the LFNST mode is applied to the current CU and/or which LFNST kernel is applied when the LFNSF is applied, and the conditions comprise a target condition corresponding to that all target TBs in a target TB set have a TS mode indication as false, and the target TB set is selected from the TBs in the current CU. The current CU is encoded or decoded according to the LFNST mode.