Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.

Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.

Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A stacked wiring structure includes a first wiring substrate and a second wiring substrate. The first wiring substrate includes a first glass substrate, multiple first conductive through vias penetrating through the first glass substrate, and a first multi-layered redistribution wiring structure disposed on the first glass substrate. The second wiring substrate includes a second glass substrate, multiple second conductive through vias penetrating through the second glass substrate, and a second multi-layered redistribution wiring structure disposed on the second glass substrate. The first conductive through vias are electrically connected to the second conductive through vias. The first glass substrate is spaced apart from the second glass substrate. The first multi-layered redistribution wiring structure is spaced apart from the second multi-layered redistribution wiring structure by the first glass substrate and the second glass substrate.

Abstract: A motor drive system includes an electric motor, a drive circuit and a control unit. The drive circuit provides a driving current to the electric motor. A current command generator of the control unit generates a current command according to a torque command and a motor operating information. The driving current is converted into a d-axis current and/or a q-axis current by the control unit. Consequently, the driving current is close to the d-axis current command and/or the q-axis current command corresponding to the current command. If a value of the torque command is positive, the current command generator generates the corresponding current command according to a MTPA lookup table. If the value of the torque command is negative, the current command generator generates the corresponding current command according to a zero recycle lookup table.

Abstract: A method includes depositing solder paste over first contact pads of a first package component. Spring connectors of a second package component are aligned to the solder paste. The solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. A device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. Each of the plurality of spring coils extends from the first package component to the second package component.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: The present invention discloses an RF element group testing system and method. The method comprises steps: adding an identification feature to a first RF signal, which is output by one of the plurality of tested RF elements, to generate an identification RF signal; synthesizing the identification RF signal and a second RF signal, which is output by each of the rest of the tested RF elements, to generate a corresponding synthesis signal; resolving the synthesis signal into the identification RF signal and the corresponding second RF signal according to the identification feature; restoring the identification RF signal into the first RF signal; and calculating at least one signal-feature parameter of the first RF signal and the second RF signal.

Abstract: A communication device for detecting an object includes a power module, an antenna array, a first sensor pad, a second sensor pad, and a control unit. The antenna array is excited by the power module, and is configured to provide a first beam group and a second beam group. The first sensor pad is disposed adjacent to the first side of the antenna array. A first capacitance is formed between the first sensor pad and the object. The second sensor pad is disposed adjacent to the second side of the antenna array. A second capacitance is formed between the second sensor pad and the object. The control unit controls the power module according to the first capacitance and the second capacitance, so as to selectively apply at least one power backoff operation to the first beam group and/or the second beam group.

Abstract: A system for testing antenna-in-package (AiP) modules and a method for using the same is disclosed. Firstly, AiP modules respectively receive RF signals from a testing transmitting antenna. Then, at least one of the power and the phase of each of the RF signals is adjusted to generate modulated RF amplified signals as recognition tags with difference. The RF amplified signals are received from each control integrated circuit (IC) and the power of the modulated RF amplified signals is summed to generate a net mixed test signal. Finally, the test signal is received and RF properties corresponding to at least one of the power and the phase of each of the RF amplified signals as recognition tags are obtained. The method can simultaneously test a plurality of AiP modules to shorten the test time.

Abstract: A device for testing a group of radio-frequency (RF) chip modules and a method for using the same is disclosed. The device includes a signal analyzer, a power divider, control ICs, a signal controller, and a power combiner. The power divider receives an RF signal and transmits RF input signals to the RF chip modules and the control ICs in response to the RF signal. The signal controller controls each control IC to adjust at least one of the power and the phase of the corresponding RF input signal, thereby generating an RF output signal. The power combiner receives the RF output signal from each control IC to generate a test signal. The signal analyzer receives the test signal and obtains RF properties corresponding to at least one of the power and the phase of each RF output signal.

Abstract: An antenna measurement system is configured to measure a radiation field pattern of an AUT fixed on a reference surface. The antenna measurement system includes an articulated robot, a measurement component, and a processor. The articulated robot is seated on a periphery of the reference surface, with a movable end capable of scanning a short-distance area defined by the reference surface. The measurement component is arranged on the movable end of the articulated robot, and a front surface of the measurement component is a specific geometric surface, which is used to face the antenna for radiation measurement. The processor is coupled to the movable end to control the movable end to drive the measurement component to move relative to the antenna along a predefined scanning path, and keep the specific geometric surface facing the antenna during the movement along the scanning path.

Abstract: An information handling system include a serial peripheral interface (SPI) flash memory device with a BIOS firmware of a platform, and a processor that may build a hand-off block for platform specific override data for the platform, and patch the BIOS base firmware image with the platform specific override data to modify the BIOS base firmware image according to the platform. The processor may also update the BIOS firmware in the SPI flash memory device with the BIOS base firmware image.

Abstract: An antenna measurement system includes an array of antennas, an array of reflectors, and a measurement surface. The array of antennas includes a plurality of antenna elements arranged in a straight line; any two adjacent antenna elements in the above antenna elements are separated by a predetermined distance, and each of the antenna elements in the above antenna elements has a radiator and a feed point. The array of reflectors includes at least one reflector and is arranged in a width direction or a height direction, and the array of reflectors is configured to generate a reflection signal according to a signal sent by the array of antennas. An antenna to be measured is configured to perform a measurement operation on the reflection signal on the measurement surface.

Abstract: Provided by the present disclosure are a power supply circuit and a charging device. The power supply circuit comprises a pulse transformer circuit and a first power supply conversion circuit. The pulse transformer circuit comprises a pulse transformer and a switch control circuit; a primary winding of the pulse transformer is connected to a power supply and is connected to the switch control circuit, and the switch control circuit is used to modulate the voltage on the primary winding into a pulse voltage; and the input terminal of the first power supply conversion circuit is connected to a secondary winding of the pulse transformer, and is used to transform the voltage on the secondary winding of the pulse transformer into a first preset voltage range when the voltage outputted by the secondary winding exceeds the first preset voltage range, and then output the voltage.